臺灣博碩士論文加值系統

隨著通訊科技的發展，近日無線通訊之需求開始朝高資料率(High Data Rate)發展，而多天線系統扮演著重要的角色，很重要的原因是通道容量(Channel Capacity)會隨著最小天線數目(傳送或接收端)而呈現線性成長，故在高資料量傳輸的應用上會比單輸入單輸出系統(Single Input Single Output, SISO)更有優勢，然而，多天線間的干擾是必須克服的問題。此外，另增LDPC Code，因為可以非常逼近夏儂極限(Shannon Limit)，所以能減少傳輸所消耗能量以及提高糾正錯誤的能力。
本論文執行了多輸入多輸出天線(Multiple Input Multiple Output, MIMO)與低密度同位元查核碼(LDPC)之編解碼系統整合之設計與實作。內容包含主要幾個部分: MIMO-OFDM理論及LDPC Codec之介紹、訊號偵測演算法及電路設計、 LLR解調變電路設計、白高斯通道雜訊模擬電路設計、MIMO-LDPC系統之整合與設計。其中訊號偵測電路使用K-最佳演算法去實作，結合廣度優先和深度優先的特質是有穩定吞吐量的一種設計，且運用列舉電路之訊號估測可比傳統K-Best使用較少的符元去擴展最佳路徑，而得到的效能仍然相當優異。
LLR解調變電路使用的是分段線性近似法，不同於傳統上使用歐幾里得距離去作LLR的運算，而使用此方法搭配LDPC解碼器的BER效能亦能有相當好的表現，使用此方法能夠使MIMO訊號偵測電路之輸出誤碼率跑到更低的點，經Matlab模擬證實可以很接近浮點數之模擬結果，此系統設計實現於44天線、64-QAM調變，當EbN0=18 dB時，可以達到10-7以下之誤碼率，最後，此MIMO訊號偵測電路於Xilinx Vertex-7 FPGA上成功進行系統驗證。

As the development of communication technology, demands of high data rates of wireless communications grow rapidly. The multiple antenna system plays an important role. The reason is that channel capacity increases linearly with the minimum number of antennas. Therefore, it has the advantage over the single input single output (SISO) system in terms of high data transmission rates. However, interference between multiple antennas needs to be overcome. In addition, low density parity check (LDPC) codec is added because it can approach the Shannon Limit and helps reduce power consumption in transmission, as well as enhance error correction capability.
In this thesis, integration and implementation of multiple input multiple output (MIMO) with LDPC codec systems are performed. They include several parts: theories of MIMO-OFDM and LDPC codec, algorithms of signal detection and circuit design, log-likelihood ratio (LLR) demodulator circuit design, additive white Gaussian noise (AWGN) generator circuit design, integration and design of MIMO-LDPC system. The signal detector was implemented by the K-Best algorithm, which combines the properties of both breadth-first and depth-first algorithms with constant throughput. In comparison with the conventional K-Best, this algorithm using enumeration circuit to obtain the estimated transmitted symbol results in less symbol numbers to expand the best K paths, while the performance is still excellent.
For the LLR demodulator, instead of the conventional LLR calculation using partial Euclidean distance (PED), the linear approximated LLR algorithm is used in the LDPC decoder. The integration of MIMO detector with LDPC decoder achieves excellent bit error rate (BER) performance. The Matlab simulation shows the fixed point results very close to the floating point results. When EbN0 = 18 dB for 64-QAM modulation with 44 antennas, the BER can be as low as 10-7. Finally, this MIMO Detector was verified using Xilinx Virtex-7 FPGA board successfully.

誌謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vii
表目錄 ix
第一章 序論 1
1.1研究背景 1
1.2研究動機 1
1.3論文架構 3
第二章 MIMO-OFDM及LDPC Codec介紹 4
2.1正交分頻多工 4
2.1.1 正交分頻多工技術介紹 5
2.1.2 OFDM系統架構 7
2.1.3保護區間和循環字首 8
2.1.4 OFDM之優缺點探討 8
2.2 多輸入多輸出系統(MIMO) 9
2.3 通道衰減(Channel Fading)探討 10
2.4 空間-時間碼及空間-頻率碼(STBC and SFBC) 11
2.5 MIMO訊號模型 14
2.6 低密度同位元查核碼 15
2.7 LDPC Encoder 16
2.8 LDPC Decoder 16
2.9 白高斯雜訊產生器(AWGN) 19
2.10 MIMO-LDPC系統整合 21
第三章 多輸入多輸出系統的訊號偵測介紹 22
3.1多輸入多輸出系統訊號偵測 22
3.1.1線性訊號偵測 22
3.1.2非線性訊號偵測 23
3.2 K-最佳演算法與樹狀搜尋 26
3.2.1 樹狀搜尋法 26
3.2.2 深度優先(Depth first)搜尋法 27
3.2.3 廣度優先(Breadth first)搜尋法 29
3.2.4 最佳優先(Best first)搜尋法 30
3.2.5 實數分解最佳優先搜尋法 31
3.3 偵測訊號輸出種類 33
3.3.1 硬性輸出(Hard output) 33
3.3.2 軟性輸出(Soft output) 33
3.4演算法優缺點分析及效能 37
第四章 K-Best列舉法及排序方法介紹 38
4.1 列舉中心點 38
4.1.1 表列舉法 38
4.1.2 實數列舉法 40
4.1.3 結合式列舉法 41
4.2排序演算法介紹 43
4.2.1 氣泡排序法 43
4.2.2 選擇排序法 44
4.2.3 平行分堆排序 45
4.2.4交錯排序法 46
4.3 軟性輸出LLR 47
4.3.1 單次LLR值 48
4.3.2 漸進式LLR值 49
4.3.3 最後階層更新LLR 50
4.3.4 LLR演算法效能比較 51
4.3.5 線性近似LLR模擬結果 52
第五章 效能模擬與電路硬體架構設計 57
5.1 硬體設計介紹及系統效能模擬 57
5.1.1 不同實數分解法之R矩陣效能模擬 58
5.1.2 MIMO Detector不同K值效能模擬 61
5.1.3 MIMO Detector與LDPC Decoder整合效能模擬 62
5.1.4 不同解調變方法之效能模擬 63
5.1.5 線性近似LLR與精確LLR效能模擬 64
5.2 MIMO訊號偵測電路 65
5.2.1前處理電路及列運算單元(Pre-Processing and Row Processing Unit) 66
5.2.2 天線間干擾消除 68
5.2.3 列舉電路 70
5.2.4 歐幾里得距離計算 73
5.2.5 LLR計算電路(解調變) 73
5.3 整體系統電路設計 77
第六章 結論與未來展望 78
參考文獻 79

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