臺灣博碩士論文加值系統

本論文說明了奈米尺度模板的製作可以透過黃光微影術及矽濕式蝕刻的結合來完成。首先利用黃光微影在絕緣層上矽(SOI)基板定義出長度50微米、寬度約10微米的矩形方框圖形，並透過矽濕式蝕刻在元件層產生V型槽結構，接著在基板背面進行矽濕式深蝕刻以露出絕緣層。
在清除氧化層後製作出的模板上奈米線縫隙，寬度範圍在300到700奈米間，長度範圍則在37到57微米間，而我們能夠製作出的縫隙最小寬度約在180奈米左右，這些模板上縫隙將會用於奈米模板微影術上，此技術讓我們在不同基板和沉積物質的選擇上更為靈活，模板還可以在清洗後重複使用。
論文第二個部分，我們將示範如何透過奈米模板微影術完成矽奈米線場效應電晶體元件的製作，製程首先將第一部分完成的模板透過奈米模板微影術製作出鎳奈米線，奈米線平均長度和寬度分別在47微米及610奈米，我們透過黃光微影在每一條鎳奈米線的兩端點定義出鎳電極區，後續經過矽乾式蝕刻、鎳的移除來完成矽奈米線與電極區部分，其中矽奈米線最小寬度在240奈米左右，我們目前進行到矽奈米線場效應電晶體的電性量測。

Fabrication of nanoscale stencil has been demonstrated by combining regular ultraviolet (UV) photolithography and anisotropic wet silicon etch. First, we use photolithography process to define rectangular patterns, whose length is around 50 m and width around 10 m, on top of a silicon-on-insulator (SOI) wafer. Then anisotropic wet silicon etch produce a V-groove in the device Si layer. After this, we performed a deep silicon wet etch on the backside substrate to reveal the insulator layer. Line-shaped slits with width between 300 to 700 nm and length between 37 to 57m reveal after oxide etch. The minimum width of the slits can be as small as 180 nm. These slits are then used to be stencils for Nano-Stencil Lithography (NSL). Using NSL, we have more flexibility to choose various substrates and depositing materials. The stencils can also be cleaned and used repeatedly.

In the second part of this dissertation, we will demonstrate how to use NSL to fabricate silicon nanowire field-effect transistors (NW-FETs). First, nickel (Ni) nanowires are fabricated by NSL with stencils fabricated using the method proposed in the first part of the dissertation. The average length and width of the fabricated Ni wires are 47m and 610 nm, respectively. After Ni nanowires fabrication, we fabricate square Ni contact pads that connected to the two ends of each nanowire using UV photolithography. Silicon nanowire connected to two contact pads reveals after dry silicon etch and Ni removal processes. The linewidth of Silicon nanowire is as narrow as 240 nm. We are currently perform electrical measurement on these fabricated Silicon NW-FETs.

摘要 I
SUMMARY III
致謝 VII
本文目錄 VIII
圖目錄 XV
表目錄 XII
第 1 章 簡介 1
1-1研究動機 1
1-2模板製程 2
1-2-1奈米模板微影術(Nano-Stencil Lithography) 2
1-2-2奈米模板製程 2
1-3奈米模板微影術製程之奈米結構 5
1-4奈米模板的可重複使用性 7
1-5模板(stencil)遮罩應用 10
1-5-1矽奈米線場效應電晶體感測PH值 12
1-5-2矽奈米線場效應電晶體感測DNA 14
1-6結論 16
第 2 章 實驗儀器與光罩設計 17
2-1製程儀器 17
2-1-1光罩對準曝光機(Mask Aligner) 17
2-1-2電漿輔助化學氣相沉積(PECVD) 20
2-1-3電子束蒸鍍機(Electron Beam Evaporation) 21
2-1-4高溫爐管 22
2-1-5感應耦合式電漿蝕刻系統 (ICP) 23
2-2量測儀器 24
2-2-1表面輪廓儀(Stylus Profiler) 24
2-2-2掃描式電子顯微鏡(Scanning Electron Microscope) 25
2-2-3電性量測系統 26
2-3光罩設計 27
2-3-1光罩設計原理 28
2-3-2奈米線場效應電晶體製程光罩 29
第 3 章 絕緣層上矽奈米尺度模板製作 31
3-1奈米尺度模板製作流程之參數分析與討論 31
3-2V型槽結構 33
3-3SOI基板上層製程 36
3-3-1絕緣層上矽(SOI)基板與光罩圖形選擇 36
3-3-2方框圖形與尺寸變化之分析 37
3-3-3上層矽蝕刻與方框尺寸變化之分析 39
3-4SOI基板底層製程 41
3-4-1聚二甲基矽氧烷(PDMS)蝕刻阻擋層與載台的使用 41
3-4-2模板上縫隙與方框的關聯 42
3-4-3爐管熱氧化與蝕刻 44
第 4 章 奈米模板微影術之應用 47
4-1奈米模板微影術 47
4-1-1金屬奈米線 47
4-1-2模板正面與背面的蒸鍍 49
4-1-3模板的重複性使用 51
4-2矽奈米線場效應電晶體 52
4-2-1製程方法 52
4-2-2矽奈米線場效應電晶體之電性分析 54
4-2-3參雜後矽奈米線場效應電晶體之電性分析 61
4-3光罩圖形─方框與電極區結合 68
第 5 章 結論與未來展望 70
5-1奈米模板 70
5-2奈米模板微影術 70
5-3未來展望 71
5-3-1感測型奈米線場效應電晶體元件 71
參考文獻 72

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