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研究生:柳延松
研究生(外文):Liu, Yen-Song
論文名稱:針對錯誤修正碼記憶元件在早夭期失效率的新式計算方式之研究
論文名稱(外文):Study of Novel Calculation of Early-Life Failure Rate for Memory Devices with Error Correction Codes
指導教授:陳智陳智引用關係
指導教授(外文):Chen, Chih
學位類別:碩士
校院名稱:國立交通大學
系所名稱:工學院碩士在職專班半導體材料與製程設備組
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:70
中文關鍵詞:錯誤修正碼早夭期失效率
外文關鍵詞:Error Correction CodesEarly-Life Failure Rate
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一般而言,產品的使用壽命可大致區分為早夭期、使用期及老化期三個時期。而對於早夭期壽命測試,其傳統的失效率計算是以單顆元件為基本計算單位來評估其早夭期壽命表現,此傳統方法若要達到一定的可靠度水準,例如:要滿足早夭期失效率每百萬個元件低於一千個失效(parts per million),即1000ppm,則元件所需要的測試數量必須相當龐大,且測試費用亦相當的高。相對地,對於搭配錯誤修正碼(Error Correction Code, ECC)的記憶體元件而言,其內部可以藉由ECC功能去修復每條字串(Word line)上的單一位元錯誤,若此搭配有ECC的元件仍使用傳統的評估計算方式,除了測試數量必須相當龐大,亦耗費相當高的測試費用,更無法表現出其ECC的修復效能。
在本文中,我們為能將搭配有ECC元件的早夭期失效率表達出來,故藉由以字串為單位來取代以單一元件為基本計算單位的觀點,進而探討早夭期壽命的新式計算方式,文章中的實驗將使用內部設計有ECC的隨機存取記憶體(Dynamic Random Access Memory, DRAM),在早夭期壽命測試的條件下進行測試,並探討信心度水(confidence level)因子與核對位元因子,進而將新式計算方式做一修正。結果顯示,此方式可更精準的估算出ECC元件的失效率。此外,我們也比較了早夭期失效率傳統與新式評估計算方式的差異。
最後,藉由此新式評估計算方式的使用來預測元件在早夭期失效率的性能表現,同時將離群產品做更進一步的分析及解釋。此外,也藉此新式評估計算方式配合測試時間的延長去找出產品在浴缸曲線(Bathtub Curve)中的早夭期失效率分布曲線。
Generally, the lifetime in a electric product includes early-life failure, useful life period and wear-out failure period. For early-life failure testing, the traditional failure rate calculation is based on a single sample as a unit to estimate product performance in early-life, if the failure rate required to meet general criteria (for example : the failure rate required less than 1000ppm(parts per million)) by the traditional calculation method. It needs huge amount of samples, and also spends expensive testing cost. On the other, for a memory device which have Error Correction Code (ECC) design inside, it can repair single bit error in a word line by ECC function in a device, if we still use traditional calculation method for ECC device, it not only spend much cost, but also can’t present the ECC repair ability and performance for ECC device.

In this paper, we want to present the early failure rate for ECC device by a novel calculation method, so we use a word line instead of a single sample as a calculation unit, then bring up and discuss the novel failure rate calculation for early life period, the experiments in this paper use a Dynamic Random Access Memory (DRAM) device with ECC design inside and stress these samples in early life time test condition. We further discuss the confidence level factor and check bit factor in this paper, then have a further correction for the novel failure rate calculation formula. The result shows the novel calculation formula can estimate the failure rate more accurately for ECC device. BTW, we also list a comparison between traditional and novel estimation method.

Finally, the novel calculation method was used to predict the early life performance for ECC device, and perform a further analyzing and explanation for outlier sample. Besides, we also use try it to find the early failure rate curve in Bathtub Curve by extending stress duration.
一、緒論...................................................1
1.1 研究動機與目的.........................................3
1.2 問題描述...............................................4
1.3 論文架構...............................................5
二、文獻回顧...............................................6
2.1 前言...................................................6
2.2 動態隨機存取記憶體結構簡介.............................7
2.3 DRAM儲存位元資料錯誤原因簡介..........................13
2.4 漢明碼的簡介..........................................16
2.4.1 漢明碼的原理....................................17
2.4.2 漢明碼編碼及錯誤偵測範例........................18
2.5 錯誤修正程式碼的優缺點比較............................20
2.6 早夭期失效率測試條件簡介..............................21
2.7 早夭期失效率的傳統計算方式簡介........................26
三、設計與實驗............................................28
3.1 早夭期失效率新式評估計算方式簡介......................28
3.2 早夭期失效率新式評估計算方式實驗......................34
四、結果與討論............................................38
4.1 因子探討與修正........................................38
4.1.1 信心水準因子的探討與新式計算方式的修正(一)......38
4.1.2 核對位元因子的探討與新式計算方式的修正(二)......40
4.1.3 修正後新式計算方式的早夭期DPPM實驗結果..........42
4.2 傳統與新式DPPM評估計算方式的優缺點比較................44
4.3 相關參數與早夭期失效率的關聯性........................50
4.4 藉由新式評估方式可對離群產品做進一步故障分析..........51
4.4.1 故障分析結果....................................53
4.4.2 離群產品真因說明................................56
4.5 藉由測試後所增加的失效位元值及產品數量判定產品製程的穩
定度..................................................62
4.6 藉由延長測試時間的浴缸曲線分布來預測產品的穩定度......64
五、結論..................................................66
參考文獻..................................................68
[1] 菊地正典,「圖解半導體」,王政友譯,初版,世茂出版社,
台北,民國九十三年。
[2] JEDEC Standard No.74A,"Early Life Failure Rate
Calculation Procedure for Semiconductor Components",
JEDEC Solid State Technology Association, Feb. 2007.
[3] Meenatchi Jagasivamani, Dong Sam Ha,"Development of
a Low-Power SRAM Compiler", pp.498-501, vol 4, IEEE
International Symposium, 2001.
[4] Chandra Mouli,"DRAM Reliability",Micron Technology,
Micron Technology Inc., Topic 223, pp.10-11, IRPS
Tutorial-2, 2005.
[5] Mitsumasa Koyanagi,"The Stacked Capacitor DRAM Cell
and Three-Dimensional Memory", Department of
Bioengineering and Robotics, Tohoku University, Japan,
pp.37-41, Solid-State Circuits Newsletter, IEEE
Journals, Jan. 2008.
[6] "International Technology Roadmap For Semiconductors
2007 Edition Executive summary", pp.4-5, ITRS 2007.
[7] Y.Aoki, et al.,"Ultra-High-Performance 0.13-um Embedded
DRAM Technology Using TiN/HfO2/TiN/W Capacitor and Bosy-
Slightly-Tied SOI", ULSI Device Development Division,
System LSI Design Engineering Division, NEC Corporation
, Japan, pp.831-834, IEDM 2002.
[8] Rick Merritt,"Microsoft says PCs may need DRAM
upgrade", EETimes, May 17, 2007.
[9] N. Seifert,"SER Fundamentals", Intel Corporation,
Topic 121, pp.63, pp.97, IRPS 2006 Tutorial-2.
[10]JEDEC Standard No. 89A,"Measurement and Reporting of
Alpha Particles and Terrestrial Cosmic Ray-Induced Soft
Errors in Semiconductor Devices", JEDEC Solid State
Technology Association, Oct. 2006.
[11]Ethan Cannon,"Characterization of Soft Errors in
Advanced Technologies", The Boeing Company, Seattle, WA
USA, S-124, pp.10, IRPS Tutorial Presentations, 2009.
[12]U. K. Kumar, B. S. Umashankar,"Improved Hamming Code
for Error Detection and Correction", Wireless Pervasive
Computing, ISWPC, pp.498-500, 2nd International
Symposium, 2007.
[13]Joint Publication(JP001.01),"Foundry Process
Qualification Guidelines (Wafer Fabrication
Manufacturing Sites)", JEDEC Solid State Technology
Association, May 2004.
[14]Nabendu Pal, Sahadeb Sarkar,「基礎統計學」,張慶暉,林
志娟譯,pp.221-227,初版,東華書局,台北,民國九十四年。

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