|
[1] 菊地正典,「圖解半導體」,王政友譯,初版,世茂出版社, 台北,民國九十三年。 [2] JEDEC Standard No.74A,"Early Life Failure Rate Calculation Procedure for Semiconductor Components", JEDEC Solid State Technology Association, Feb. 2007. [3] Meenatchi Jagasivamani, Dong Sam Ha,"Development of a Low-Power SRAM Compiler", pp.498-501, vol 4, IEEE International Symposium, 2001. [4] Chandra Mouli,"DRAM Reliability",Micron Technology, Micron Technology Inc., Topic 223, pp.10-11, IRPS Tutorial-2, 2005. [5] Mitsumasa Koyanagi,"The Stacked Capacitor DRAM Cell and Three-Dimensional Memory", Department of Bioengineering and Robotics, Tohoku University, Japan, pp.37-41, Solid-State Circuits Newsletter, IEEE Journals, Jan. 2008. [6] "International Technology Roadmap For Semiconductors 2007 Edition Executive summary", pp.4-5, ITRS 2007. [7] Y.Aoki, et al.,"Ultra-High-Performance 0.13-um Embedded DRAM Technology Using TiN/HfO2/TiN/W Capacitor and Bosy- Slightly-Tied SOI", ULSI Device Development Division, System LSI Design Engineering Division, NEC Corporation , Japan, pp.831-834, IEDM 2002. [8] Rick Merritt,"Microsoft says PCs may need DRAM upgrade", EETimes, May 17, 2007. [9] N. Seifert,"SER Fundamentals", Intel Corporation, Topic 121, pp.63, pp.97, IRPS 2006 Tutorial-2. [10]JEDEC Standard No. 89A,"Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices", JEDEC Solid State Technology Association, Oct. 2006. [11]Ethan Cannon,"Characterization of Soft Errors in Advanced Technologies", The Boeing Company, Seattle, WA USA, S-124, pp.10, IRPS Tutorial Presentations, 2009. [12]U. K. Kumar, B. S. Umashankar,"Improved Hamming Code for Error Detection and Correction", Wireless Pervasive Computing, ISWPC, pp.498-500, 2nd International Symposium, 2007. [13]Joint Publication(JP001.01),"Foundry Process Qualification Guidelines (Wafer Fabrication Manufacturing Sites)", JEDEC Solid State Technology Association, May 2004. [14]Nabendu Pal, Sahadeb Sarkar,「基礎統計學」,張慶暉,林 志娟譯,pp.221-227,初版,東華書局,台北,民國九十四年。
|