臺灣博碩士論文加值系統

本論文中討論以TSMC 1P6M 0.18 μm CMOS製程，實現一個十位元、每秒兩千萬次取樣時間之逐漸逼近式類比數位轉換器。十位元類比數位轉換器中的數位類比轉換器為了有較高的準確度，使用二進位加權電容陣列
，並採用所提出之單端DAC切換技巧來降低切換能量和電容面積，取樣保持電路包含靴帶式電路以提升取樣開關線性度。兩級的動態比較器有較佳的電壓偏移。非同步式控制邏輯可以避免使用額外高速之外部時脈，並有效分配比較周期所需時間。
經由HSPICE和SpectreRF輔助設計軟體驗證，結果在供應電壓為1.8 伏特下，量測差分非線性度及積分非線性度為 1.2 LSB和1.54 LSB。當輸入訊號為10 KHz下，其量測所得有效位元為8.85-bit，本晶片面積包含ESD PADs為0.57 mm2，整體電路功率消耗為910 μW。

This paper presents a 1.8-V 10-bit 20MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in the TSMC 0.18-um CMOS process. By applying a single-sided switching method that reduces DAC switching energy, the proposed SAR ADC achieves lower power consumption. In order to avoid using an external high frequency clock to drive the ADC, asynchronous control logic is used. A pre-amplifier based comparator reduces the kickback noise from the logic circuit. A bootstrapped switch increases the sample linearity of the ADC.

The SAR ADCs were simulated by HSPICE and SpectreRF. The 10-bit ADC was taped out by TSMC. The measured results for differential and integral nonlinearity of the 10-bit ADC are within 1.2/-0.4 LSB (Least Significant Bit) and -1.54~1.1LSB respectively at full sampling rate. The measurement results show an effective number of bits (ENOB) of 8.85-bits with a sampling frequency of 20 MHz at a 10 KHz input frequency. The chip area, including pads, is 0.57 mm2. Power consumption of this ADC is 910μW with a 1.8 V supply voltage.

Abstract(in Chinese) II
Abstract(in English) III
Contents IV
List of Figures VI
List of Tables X

CHAPTER 1 Introduction 1
1.1 Motivation 1
1.2 Focus and Contributions 2
1.3 Organization of This Thesis 3

CHAPTER 2 Fundamentals of Analog-to-Digital Converter 4
2.1 Introduction 4
2.2 Basic Concepts 4
2.2.1 Differential Nonlinearity (DNL) 4
2.2.2 Offset Error 5
2.2.3 Gain Error 6
2.2.4 Missing Codes 6
2.2.5 Integral Nonlinearity (INL) 7
2.2.6 Signal-to-Noise Ratio (SNR) 7
2.2.7 Signal-to-Noise and Distortions Ratio (SNDR) 8
2.2.8 Spurious Free Dynamic Range(SFDR) 8
2.2.9 Resolution and Effective Number of Bits (ENOB) 8
2.2.10 Coherent Sampling 9
2.3 Architectures of Analog-to-Digital Converters 9
2.3.1 Flash ADC 9
2.3.2 Two-Step Flash ADC 10
2.3.3 Time-Interleaved ADC 11
2.3.4 Pipelined ADC 12
2.3.5 Successive Approximation ADC 13
2.3.6 Sigma-Delta ADC 14
2.3.7 Conclusion 15
2.4 Papers’ Survey 15
2.5 Summary 21
CHAPTER 3 Energy Efficient DAC Switching Method 22

3.1 Introduction 22
3.2 Conventional SAR ADC 23
3.3 Proposed SAR ADC 25
3.4 Analysis of Switching Energy In DAC Network 27
3.5 Summry 33
CHAPTER 4 Chip Design of 10-bit 20-MS/s SAR ADC 34
4.1 Introduction 34
4.2 The 10-bit 20-MS/s SAR ADC architecture 34
4.3 Circuit Level Design 35
4.3.1 Sample and Hold Circuit 35
4.3.2 Comparator 41
4.3.2.a Architecture 43
4.3.2.b Specification 45
4.3.2.c Simulation results 46
4.3.3 Digital to Analog Converter 48
4.3.3.a Charge Redistribution DAC 48
4.3.3.b KT/C noise 50
4.3.3.c Capacitor matching 50
4.3.4.d Placement of Capacitors 52
4.3.4 SAR Control Logic Circuit 52
4.3.4.a Synchronous SAR Controller 52
4.3.4.b Asynchronous SAR Controller 53
4.3.4.c Proposed Asynchronous SAR Controller 54
4.3.5 Switching Logic 56
4.3.6 Digital Buffer Circuit 56
4.4 Simulation Results 59
4.5 Measurement Results 64
4.5.1 Measurement Considerations 64
4.5.2 Chip Floor Plan and PCB Design 65
4.5.3 Measurement Instruments 67
4.5.4 Measurement Results 68
4.6 Conclusions 71
CHAPTER 5 Conclusions and Future Work 72
5.1 Conclusions 72
5.2 Future Work 73
References 74
Appendix 76

[1]C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol 45, no. 4, pp. 731-740, Apr. 2010.
[2]Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu and Ying-Zu Lin, "10-bit 30-MS/s SAR ADC Using a Switchback Switching Method," IEEE Transactions on VLSI Systems, vol. 21, no. 3, pp.584-588, Mar. 2013. (SCI, EI)
[3]Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu and Guan-Ying Huang, "An Asynchronous Binary-Search ADC Architecture with a Reduced Comparator Count," IEEE Transactions on Circuits and Systems - I, vol. 57, no. 8, pp.1829-1837, Aug. 2010. (SCI, EI)
[4]Hariprasath, V., Guerber, J., Lee, S.-H., and Moon, U.-K. “Merged capacitor switching based SAR ADC with highest switching energy efficiency,” Electron. Lett., 2010,46,(9), pp. 620-621.
[5]C.Yuan and Y.Lam., “Low-energy and area-efficient tri-level switching scheme for SAR ADC,” Electron. Lett., 2012,48,(9), pp. 482-483.
[6]G.-Y. Huang, C.-C. Liu, Y.-Z. Lin, and S.-J. Chang, “A 10-bit 12 MS/ssuccessive approximation ADC with 1.2-pF input capacitance,” in IEEE ASSCC Dig. Tech. Papers, Nov. 2009, pp. 157–160.
[7]Sang-Pil Nam, Yong-Min Kim, Dong-Hyun Hwang, Hyo-Jin Kim, Tai-Ji An, Jun-Sang Park, Suk-Hee Cho, Gil Cho Ahn and Seung-Hoon Lee, “A 10-bit 1 MS/s-to-10MS/s 0.11um CMOS SAR ADC for Analog TV Applications,” international Soc Design Conference (ISOCC), pp.142-147, Nov.4-7,2012.
[8]Allen, P.E., and Holberg, D.R.: ‘CMOS Analog Circuit Design’ (Oxford University Press, Inc., New York, USA, 2002, 2nd Edn.)
[9]Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto and T. Kuroda,“Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC,” CICC, pp. 279-282, Sep. 2009.
[10]Ting Yang, Li Zhiqun, “A 7-bit 26-MS/s SAR ADC in 0.18um CMOS process for WSN application,” High speed Intelligent Communication Forum(HSIC), 2012 4th international, pp.1-4, May. 2012.
[11]Zhuang Zhaodong, Li Zhiqun, "A 7-bit 16-MS/s low-power CMOS pipeline ADC," Communication Technology (ICCT), 2011 IEEE 13th international Conference, pp.1082-1085, Sept. 2011.