臺灣博碩士論文加值系統

在本論文中，我們提出兩種新穎具多重閘極與奈米柱之無電容式單電晶體動態隨機存取記憶體(Capacitorless One-Transistor Dynamic Random Access Memory, 1T-DRAM)：第一種我們提出具有鰭式閘極與柱狀本體(Fin-Gate and Pillar-Body, FGPB)之雙閘極奈米線薄膜電晶體元件(Double-Gate Nanowire Thin-Film Transistor)。第二種我們提出具有環繞式閘極與奈米柱(Gate-All-Around and Nano-Pillar, GAANP)之垂直式電流橋電晶體元件(Vertical Current Bridge MOSFET)。
首先我們使用閘極引致汲極漏電流機制(Gate-Induced Drain-Leakage, GIDL)做為資料寫入機制，並藉由Sentaurus TCAD 12.0軟體工具來設計元件架構與驗證記憶體表現。
相較於傳統無奈米柱本體之雙閘極奈米線薄膜電晶體(Conv. DG-NTFT)元件，第一種FGPB元件由於具有奈米柱本體結構，在不佔用額外面積下能讓元件內部假中性區(Pseudo Neutral Region)增加。此能提升能帶對能帶穿隧率，且讓儲存的過量電洞能遠離元件P-N接面，所以FGPB元件的GIDL電流能提升達274.33 %；在架構搭配鰭式閘極的輔助下，可以有效增強過量電洞的控制能力，並間接克服Shockley-Read-Hall (SRH)複合的影響。低功率應用方面，元件功率消耗可維持在0.8 μW/μm以下。
第二種GAANP元件採用矽覆絕緣/塊體矽(Silicon-on-Insulator/ Bulk-Silicon)兩種基板。相較於其他橫向式電流橋1T-DRAM，由於元件具有環繞式閘極，能提升對過量電洞的控制力；元件本身具有垂直式通道，不僅能將元件建立在長通道，也能保有一定的記憶體性能。在電流橋元件邊際效益中，GAANP SOI 1T-DRAM的可程式規劃視窗(Programming Window, PW)最少能達到238.54 %的改善，以及在358 K環境下的資料保存時間(Data Retention Time, RT)也可達到6.91 %的改善。
我們所提出的兩種新穎元件不僅都能達到低功率消耗，且擁有足夠的操作容忍度和干擾抵抗能力，這對未來1T-DRAM應用提供兩項極具潛力的解決方案。

In this thesis, we propose two novel capacitorless 1T-DRAMs, with the multi-gate and nano-pillar structures : The first type is a double-gate Nanowire TFT, with the fin-gate and pillar-body structure (FGPB). The second type is a vertical current bridge MOSFET, with the gate-all-around and nano-pillar structure (GAANP).
We adopt the GIDL mechanism as 1T-DRAM programming method, and use the Sentaurus TCAD 12.0 simulation tool to confirm the memory performance.
Compared with the conv. DG-NTFT, the FGPB device has nano-pillar structure, which can increase the pseudo neutral region without additional occupied area. This structure can improve the band-to-band tunneling, and keep the holes away from the P-N junction. The GIDL current is improved about 274.33 %. With fin-gate to control the excess hole efficiently, this structure can also overcome the SRH recombination influence indirectly. In terms of the low-power application, and the power consumption can maintained below 0.8 μW/μm.
Compared with the lateral current bridge 1T-DRAMs, the GAANP SOI/Bulk-Silicon device has surrounding gate, which can enhance the excess hole control-ability; the vertical channel not only keeps the device in long-channel, but also maintains at a certain level of memory performance. In terms of the current bridge devices benchmark comparison, the GAANP SOI 1T-DRAM PW is improved at least about 238.54 %. The RT at 358 K is improved about 6.91 %.
Two novel devices not only achieve low-power consumption, but also have sufficient operating endurance and disturbance immunity. We provide two excellent candidates for future 1T-DRAM applications.

第一章 導論 1
1.1 研究背景 1
1.2 無電容式1T-DRAM文獻回顧 4
1.2.1 雙閘極薄膜電晶體元件系列 4
1.2.2 橫向式電流橋電晶體元件系列 7
1.3 動機 11
1.4 論文架構 12
第二章 操作原理 13
2.1 浮體效應 13
2.2 記憶體資料寫入機制 14
第三章 元件製作 20
3.1 模擬元件說明 20
3.1.1 具鰭式閘極與柱狀本體之雙閘極奈米線薄膜電晶體 20
3.1.2 具環繞式閘極與奈米柱之垂直式電流橋電晶體 22
3.2 元件實作 24
第四章 研究方法與結果討論 27
4.1 研究方法 27
4.2 電性探討 30
4.2.1 元件特性說明 30
4.2.2 元件輸入特性曲線暨消耗功率 35
4.2.3 元件輸出特性曲線 40
4.3 可程式規劃視窗 (Programming Window) 42
4.4 資料保存時間 (Data Retention Time) 62
4.5 溫度影響 (Temperature Influence) 66
4.6 元件容忍度 (Endurance) 70
4.7 干擾抵抗性 (Disturbance Immunity) 74
4.8 微縮化探討 (Scalability) 80
4.9 近年各1T-DRAM論文之邊際比較 (Benchmark Comparison) 80
4.10 元件實作結果與量測 (Experimental Results) 88
第五章 結論與未來發展 91
5.1 結論 91
5.2 未來發展 93
參考文獻 94
附錄一 – 微縮化物理現象 100
附錄二 – 實作檢討與討論 105
附錄三 – 模擬方法─校準 106
附錄四 – 平帶電壓與寫入偏壓關係 108
論文著述 109

[1]G. E. Moore, “Cramming more components onto integrated circuits,” Proc. IEEE, vol. 86, no. 1, pp. 82-85, Jan. 1998.
[2]K. Kim, C.-G. Hwang, and J.-G. Lee,“DRAM Technology Perspective for Gigabit Era,”IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 598-608, Mar. 1998.
[3]A. Nitayama, Y. Kohyama, and K. Hieda, “Future directions for DRAM memory cell technology,” in Proc. Int. Electron Devices Meeting (IEDM) Tech. Dig., 1998,
pp. 355–358.
[4]L. Nesbit, J. Alsmeier, B. Chen, J. Debrosse, P. Fahey, M. Gall, J. Gambino, S. Gernhardt, H. Ishiuchi, R. Kleinhenz, J. Mandelman, T. Mii, M. Morikado, A. Nitayama, S. Parke, H. Wong, and G. Bronner, “A 0.6 μm2 256Mb Trench DRAM Cell with Self-Aligned BuriED Strap (BEST),” in IEDM Tech. Dig., Dec. 5-8, 1993, pp. 627-630.
[5]T. Kaga, T. Kure, H. Shinriki, Y. Kawamoto, F. Murai, T. Nishida, Y. Nakagome, D. Hisamoto, T. Kisu, E. Takeda, and K. Itoh, “Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAMs,” IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 255-261, Feb. 1991.
[6]H.-J. Wann and C. Hu, “A Capacitorless DRAM Cell on SOI Substrate,” in IEDM Tech. Dig., 1933, pp. 635-638.
[7]S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, “A SOI Capacitor-less 1T-DRAM Concept,” in Proc. IEEE Int. SOI Conf., Oct. 2001 , pp. 153-154.
[8]P. Fazan, S. Okhonin, M. Nagoga, J. M. Sallese, L. Portmann, R. Ferrant, M. Kayal, M. Pastre, M. Blagojevic, A. Borschberg, and M. Declercq, “Capacitor-Less 1-Transistor DRAM,” in Proc. IEEE Int. SOI Conf., Oct. 7-10, 2002, pp.10-13.
[9]R. Ranica, A. Villaret, P. Mazoyer, D. Lenoble, P. Candelier, F. Jacquet, P. Masson, R. Bouchakour, R. Foumel, J. P. Schoellkopf, and T. Skotnicki, “A One Transistor Cell on Bulk Substrate (1T-Bulk) for Low-cost and High Density eDRAM,” in VLSI Symp. Tech. Dig., Jun. 2004, pp. 128-129.
[10]M. G. Ertosun, H. Cho, P. Kapur, and K. C. Saraswat, “A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM,” IEEE Electron Device Lett., vol. 29, no. 6, pp. 615-617, May 2008.
[11]S. Kim, S.-J. Choi, D.-Il. Moon, and Y.-K. Choi “Carrier Lifetime Engineering for Floating-Body Cell Memory,” IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 367-373, Feb. 2012.
[12]T. Tanaka, E. Yoshida, and T. Miyashita, “Scalability Study on A Capacitorless 1T-DRAM: from Single-gate PD-SOI to Double-gate FinDRAM,” in IEDM Tech. Dig., 2004, pp. 919-922.
[13]J.-W. Han, S.-W. Ryu, D.-H. Kim, C.-J. Kim, S. Kim, D.-Il. Moon, S.-J. Choi, and Y.-K. Choi, “Fully Depleted Polysilicon TFTs for Capacitorless 1T-DRAM,” IEEE Electron Device Lett., vol. 30, no. 7, pp. 742-744, Jul. 2009.
[14]S. Eminente, S. Cristoloveanu, R. Clerc, A. Ohata, and G. Ghibaubo, “Ultra-thin fully-depleted SOI MOSFETs: special charge properties and coupling effects,” Solid-State Electron., vol. 51, no. 2, pp. 239-244, Feb. 2007.
[15]W. Lee and W.-Y. Choi, “A Novel Capacitorless 1T-DRAM Cell for Data Retention Time Improvement,” IEEE Trans. on Nanotechnology, vol. 10, no. 3, pp. 462-466, May 2011.
[16]N. Butt and M. Alam, “Scaling Limits of double-gate and surrounding-gate Z-RAM cells,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2255-2262, Sep. 2007.
[17]N. Rodriguez, S. Cristoloveamu, and F. Gamiz, “Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible with Bulk and SOI Substrates,” IEEE Electron Device Lett., vol. 58, no. 8, pp. 2371-2377, Aug. 2011.
[18]J.-T. Lin, P.-H. Lin, Y.-C. Eng, and Y.-R. Chen, “Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure,” IEEE Trans. Electron Devices, vol. 60, no. 6, pp. 1872-1877, Jun. 2013.
[19]S. Lee, J. S. Shin, J. Jang, H. Bae, D. Yun, J. Lee, D. H. Kim, and D. M. Kim, “A Novel Capacitorless DRAM Cell Using Superlattice BandGap-Engineered (SBE) Structure With 30-nm Channel Length,” IEEE Trans. on Nanotechnology, vol. 10, no. 5, pp. 1023-1030, Sep. 2011.
[20]A. Pal, A. Nainani, S. Gupta, and K. C. Saraswat, “Performance Improvement of One-Transistor DRAM by Band Engineering,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 29-31, Jan. 2012.
[21]J. S. Shin, H. Bae, J. Jang, D. Yun, J. Lee, E. Hong, D. H. Kim, and D. M. Kim, “A novel double HBT-based capacitorless 1T DRAM cell with Si/SiGe heterojunctions,” IEEE Electron Device Lett., vol. 32, no. 7, pp. 850-852, Jul. 2011.
[22]S.-W. Ryu, J.-W. Han, C.-J. Kim, and Y.-K. Choi, “Investigation of Isolation-Dielectric Effects of PDSOI FinFET on Capacitorless 1T-DRAM,” IEEE Trans. Electron Devices, vol. 56, no. 12, pp. 3232-3235, Dec. 2009.
[23]D.-Il. Moon, J.-Y. Kim, J.-B. Moon, D.-O. Kim, and Y.-K. Choi, “Evolution of Unified-RAM: 1T-DRAM and BE-SONOS Built on a Highly Scaled Vertical Channel,” IEEE Trans. Electron Devices, vol. 61, no. 1, pp. 60-65, Jan. 2014.
[24]J.-T. Lin, P.-H. Lin, S. W. Haga, Y.-C. Wang, and D.-R. Lu, “Transient and Thermal Analysis on Disturbance Immunity for 4F2 Surrounding Gate 1T-DRAM With Wide Trenched Body,” IEEE Trans. Electron Devices, vol. 62, no. 1, pp. 61-68, Jan. 2015.
[25]J.-W. Han, S.-W. Ryu, S.-J. Choi, and Y.-K. Choi, “Gate-induced Drain-leakage (GIDL) Programming Method for Soft-programming-free Operation in Unified RAM (URAM),”IEEE Electron Device Lett., vol. 30, no. 2, pp. 189-191, Feb. 2009.
[26]J.-W. Han, S.-W. Ryu, D.-H. Kim, and Y.-K. Choi, “Polysilicon Channel TFT With Separated Double-Gate for Unified RAM (URAM)─Unified Function for Nonvolatile SONOS Flash and High-Speed Capacitorless 1T-DRAM,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 601-607, Mar. 2010.
[27]N. Rodriguez, F. Gamiz, and S. Cristoloveanu, “A-RAM Memory Cell: Concept and Operation,” IEEE Electron Device Lett., vol. 31, no. 9, pp. 972-974, Sep. 2010.
[28]N. Rodriguez, C. Navarro, F. Gamiz, F. Andrieu, O. Faynot, and S. Cristoloveanu, “Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator,” IEEE Electron Device Lett., vol. 33, no. 12, pp. 1717-1719, Dec. 2012.
[29]F. Gamiz, N. Rodriguez, and S. Cristoloveanu, “3D Trigate 1T-DRAM Memory Cell for 2x nm Node,” in IEEE Int. Memory Workshop Conf., May 2012, pp. 1-4.
[30]M. Lee, T. Moon, and S. Kim, “Floating Body Effect in Partially Depleted Silicon Nanowire Transistors and Potential Capacitor-Less One-Transistor DRAM Applications,” IEEE Trans. on Nanotechnology, vol. 11, no. 2, pp. 355-359, Mar. 2012.
[31]D.-Il. Moon, S.-J. Choi, J.-W. Han, and Y.-K. Choi, “An Optically Assisted Program Method for Capacitorless 1T-DRAM,” IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1714-1718, Jul. 2010.
[32]M. G. Ertosun, K.–Y. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat, “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electrons,” IEEE Electron Device Lett., vol. 31, no. 5, pp. 405-407, May 2010.
[33]J.-S. Shin, H. Choi, H. Bae, J. Jang, D. Yun, E. Hong, D.-H. Kim, and D.-M. Kim, “Vertical-Gate Si-SGe Double-HBT-Based Capacitorless 1T DRAM Cell for Extended Retention Time at Low Latch Voltage,” IEEE Electron Device Lett., vol. 33, no. 2, pp. 134-136, Feb. 2012.
[34]S. Okhonin, M. Nagoga, E. Carman, R. Begffa, E. Faraon,“New Generation of Z-RAM,”in IEDM Tech. Dig., Dec. 2007, pp. 925-928.
[35]H. Jeong, K.-W. Song, I. H. Park, T.-H. Kim, Y. S. Lee, S.-G. Kim, J. Seo, K. Cho, K. Lee, H. Shin, J. D. Lee, and B.-G. Park, “A New Capacitorless 1T DRAM Cell：Surrounding Gate MOSFET with Vertical Channel (SGVC Cell),” IEEE Trans. on Nanotechnology, vol. 6, no. 3, pp. 352-357, May 2007.
[36]J. P. Colinge, “Reduction of Kink Effect in Thin-Film SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 9, no. 2, pp. 97-99, Feb. 1988.
[37]E. Yoshida, and T. Tanaka, “A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 692-697, Apr. 2006.
[38]J.-H. Chen, S.-C. Wong, and Y.-H. Wang, “An Analytic Three-Terminal Band-to-Band Tunneling Model on GIDL in MOSFET,” IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1400-1405, Jul. 2001.
[39]S. Cristoloveanu, “Silicon on insulator technologies and devices: from present to future,” Solid-State Electron., vol. 45, no. 8, pp. 1403-1411, Aug. 2001.
[40]K.-H. Park, Y. M. Kim, H.-I. Kwon, S. H. Kong, and J.-H. Lee, “Fully Depleted Double-Gate 1T-DRAM Cell with NVM Function for High Performance and High Density Embedded DRAM,” in IEEE Int. Memory Workshop Conf., May 2009, pp. 1-2.
[41]M. Aoulaiche, A. Bravaix, E. Simoen, C. Caillat, M. Cho, L. Witters, P. Blomme, P. Fazan, G. Groeseneken, and M. Jurczak, “Endurance of One Transistor Floating Body RAM on UTBOX SOI,” IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 801-805, Mar. 2014.
[42]K.-W. Song, H. Jeong, J.-W. Lee, S. I. Hong, N.-K. Tak, Y.-T. Kim, Y. L. Choi, H. S. Joo, S. H. Kim, H. J. Song, Y. C. Oh, W.-S. Kim, Y.-T. Lee, K. Oh, and C. Kim, “55 nm Capacitor-less 1T DRAM Cell Transistor with Non-Overlap Structure,” in Proc. IEEE IEDM, Dec. 2008, pp. 1–4.
[43]J.-W. Han, D.-Il. Moon, D.-H. Kim, and Y.-K. Choi, “Parasitic BJT Read Method for High-Performance Capacitorless 1T-DRAM Mode in Unified RAM,” IEEE Electron Device Lett., vol. 30, no. 10, pp. 1108–1110, Oct. 2009.
[44]S.-J. Choi, J.-W. Han, D.-Il. Moon, and Y.-K. Choi, “Analysis and Evaluation of a BJT-Based 1T-DRAM,” IEEE Electron Device Lett., vol. 31, no. 5, pp. 393–395, May 2010.
[45]H. I. Hanafi, T. Kanarsky, S. Schmitz, and K. Hathorn, “Data Retention in SOI-DRAM with Trench Capacitor Cell,” in Proc. Solid-State Device Research Conference, Sep. 1998, pp. 276–279.
[46]J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nature Nanotechnology., vol. 5, no. 3, pp. 225–229, Feb. 2010.
[47]L. M. Almeida, K. R. A. Sasaki, C. Caillat, M. Aoulaiche, N. Collaert, M. Jurczak, E. Simoen, C. Claeys, and J. A. Martino, “Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM,” Solid-State Electron., vol. 90, pp. 149–154, Dec. 2013.
[48](2013). The International Technology Roadmap for Semiconductors (ITRS)-Table PIDS6. [Online]. Available: http://www.itrs.net/Links/2013ITRS/2013Tables/PIDS_2013Tables.xlsx
[49]Sentaurus User’s Manual, ver. H-2013.03, Synopsys, Inc., Mountain View, CA, USA, Mar. 2013.
[50]J.-J Maa, and C.-Y. Wu, “A new constant-field scaling theory for MOSFET’s,” IEEE Trans. Electron Devices, vol. 42, no. 7, pp. 1262-1268, Jul. 1995.
[51]J.-W. Han, S.-W. Ryu, S. Kim, C.-J. Kim, J.-H. Ahn, S.-J. Choi, K. J. Choi, J. C. Byung, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, C. P. Yun, J. W. Kim, and Y.-K. Choi, “Energy band engineering unidied-RAM (URAM) for multi-functioning 1T-DRAM and NVM,” in Proc. IEEE IEDM, Dec. 2008, pp. 1–4.
[52]A. Pal, A. Nainani, Z. Ye, X. Bao, E. Sanchez, and K. C. Saraswat, “Electrical Characterization of GaP-Silicon Interface for Memory and Transistor Applications,” IEEE Trans. Electron Devices, vol. 60, no. 7, pp. 2238-2245, Jul. 2013.
[53]J. Mitard, L. Witters, H. Arimura, Y. Sasaki, A. P. Milenin, R. Loo, A. Hikavyy, G. Eneman, P. Lagrain, H. Mertens, S. Sioncke, C. Vrancken, H. Bender, K. Barla, N. Horiguchi, A. Mocuta, N. Collaert, and A. V.-Y. Thean, “First demonstration of 15nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain,” in Proc. IEEE IEDM, Dec. 2014, pp. 16.5.1–16.5.4.
[54]K. Mondal and P. Dutta, “Big data parallelism: Challenges in different computational paradigms,” in Proc. Computer, Communication, Control and Information Technology, Feb. 2015, pp. 1-5.
[55]P. Kerber, Q. Zhang, S. Koswatta, and A. Bryant, “GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications,” IEEE Electron Device Lett., vol. 34, no. 1, pp. 6-8, Jan. 2013.