COVER
TABLE OF CONTENTS
ABSTRACT (IN CHINESE)
ABSTRACT (IN ENGLISH)
ACKNOWLEDGEMENTS (IN CHINESE)
ACKNOWLEDGEMENTS (IN ENGLISH)
LIST OF ABBREVIATIONS
LIST OF TABLES
LIST OF FIGURES
CHAPTER 1 INTRODUCTION
1.1 Introduction to the Computation of DST/DCT via the PDC Algorithm
1.2 Introduction to Signed-digit Systolic Multipliers
1.3 Sturcture of this Dissertation
References
CHAPTER 2 THE INTRINSIC PROPERTIES OF THE DST AND DCT
2.1 Introduction
2.2 Basic Lemmas
2.3 Intrinsic Properties of the Type-III DST and DCT
2.4 Summary
References
CHAPTER 3 THE PDC ALGORITHM FOR IMPLEMENTING THE DST AND DCT
3.1 Introduction
3.2 The PDC Algorithm for Implementing the DST-III/DCT-III
3.3 Summary
References
CHAPTER 4 HARDWARE REALIZATION FOR THE DST AND DCT WITH THE PDC ALGORITHM
4.1 Introduction
4.2 Hardware Implementation for the Types III and IV of Both DST and DCT
4.2.1 The Data maps and Sign-bit Multiplications (DMSMs)
4.2.2 The PDC Structure (PDCS)
4.3 The Comparison of Computational Complexity with other Methods
4.4 Summary
References
CHAPTER 5 QUANTIZATION ERROR ANALYSIS FOR IMPLEMENTING THE DST AND DCT WITH THE PDC ALGORITHM
5.1 Introduction
5.2 Quantization Error Analysis
5.3 Simulation Results]
5.4 Summary
References
CHAPTER 6 SIGNED-DIGIT SYSTOLOC MULTIPLIERS
6.1 Introduction
6.2 Definition of Basic Functins
6.3 Architecture
6.4 Application to Implement the Computation of the DST and DCT
6.4.1 The Conversion from the Decimal Number System to the Signed-digit Ternary Number System
6.4.2 The Comparison between the Signed-digit Ternary Cocd and the Signed-2''s-complement Representation
6.4.3 Implement the Computation of the DST and DCT Using the Signed-digit Systolic Multipliers
6.5 Summary
References
CHAPTER 7 CONCLUSIONS AND THE FUTURE STUDIES
7.1 Conclusions]
7.2 Future Research Topics
References
PUBLICATION LIST
VITA
|