臺灣博碩士論文加值系統

本論文中，將針對非對稱性數位用戶迴路（ADSL）之CAP架構提出一個以Barker Code為訓練序列(training sequence)的自動增益控制系統，此架構的好處是利用Barker Code擁有大的PSR之特性，輕易取得振幅以及通道延遲的信號，其中振幅的信號可以提供自動增益控制系統收斂使用，而通道延遲的信號可以提供等化器使用。
電路設計上，我們採用聯華電子之0.5微米DPDM互補式金氧半場效電晶體製程，對系統進行設計及佈局，並以3伏特電壓為其電壓源。電路主要包含了forward path的可調式增益放大器、帶通濾波器以及緩衝增益輸出級，回授路徑的Barker Code偵測器，數位/類比轉換器以及積分器。
在forward path中，可調式增益放大器由電流平方電路及四級放大器所組成，可調變的增益範圍為56dB，而且在最差的情況下，-3dB頻寬可達1x百萬赫茲，總諧失真(Total Harmonic Distortion)低於-66分貝。帶通濾波器是由一個四階Chebyshev高通濾波器及一個八階Elliptic低通濾波器所組成，頻帶位於100千赫茲到500千赫茲，頻帶內的漣波小於1分貝。兩者電路中的電阻皆以Double MOSFET電阻來完成。為了對抗製程變異以及溫度飄移，在帶通濾波器中，我們額外加入Double MOSFET電阻控制電路，由模擬結果得出，在最大的製程變異以及0oC到80oC的溫度飄移下，頻帶兩個邊緣的變異不超過1.5%。為了將帶通濾波器輸出的信號放大並輸出至晶片之外，我們設計了一個緩衝增益輸出級，在輸出腳寄生電容負載之下，-3dB頻寬可達1x百萬赫玆，於輸出2伏特峰值-峰值電壓信號時，其總諧失真低於-68分貝，。
在回授路徑中，Barker Code偵測器接收經由晶片外10位元類比/數位轉換器而來的數位信號，由自動相關(auto-correlation)及尋找最大(search maximum)電路產生振幅信號，經由6位元數位/類比轉換器，將數位信號轉換為類比信號，再經由積分器，回授控制可調式增益放大器。

In this thesis, we propose an Automatic Gain Control (AGC) system using Barker code as its training sequence for Asynchronous Digital Subscriber Loop (ADSL). The advantage of this architecture is that Barker code has the characteristic of large Peak-Side-lobe Ratio (PSR). We can easily get the information of the amplitude and the channel delay. The amplitude information is useful for the convergence of the AGC system, and the channel delay information can be provided to the equalizer.
We adopt UMC 0.5um DPDM 3v CMOS technology to design and layout our circuits. The AGC mainly is composed of forward path, such as Variable Gain Amplifier (VGA), Band-Pass Filter (BPF), and Gain & Buffer stage as well as feedback path, like Barker code detector, DAC, and integrator.
In forward path, VGA is composed of a current squaring circuit and four stages of main amplifier. The gain dynamic range of the VGA is 58db and the bandwidth is up to 20 MHz in the worst case. Besides, the total harmonic distortion is less than -66db. BPF is composed of a fourth order Chebyshev high-pass filter as well as an eighth order Elliptic low-pass filter. The bandwidth of the BPF is from 100 kHz to 500 kHz and the ripple in the pass-band must be less than 1db. Double MOSFET resistors are employed instead of the resistors in the filters. In order to overcome the process variation and thermal drift, an additional double MOSFET resistor tuning circuit is adopted. From the simulation result, the variance of the two spectrum edge is less than 1.5% in the greatest process variation and the thermal drift from 0oC to 80oC. To amplify the output of the BPF and drive it out of the chip, we design a gain & buffer stage. The cut-off frequency is up to 10 MHz with the parasitic capacitance loads of the output pads, and the THD is better than -68db when the output voltage signal is 2vpp.
In feedback path, the barker code detector receives the digital signal from the external 10-bits ADC. The auto-correlation and maximum searching circuits generate the amplitude information. Then the digital signal is converted to an analogical one by 6-bits DAC. Via the integrator, we integrate the analog from DAC and feed to VGA to control the gain.

Chapter 1 Introduction ………………………………… 1
1.1 Introduction ………………………………………………. 1
1.2 Motivation ………………………………………………… 3
1.3 Organization of the Thesis ……………………………… 4
Chapter 2 Automatic Gain Control Architecture ……. 6
2.1 Introduction to Transceiver Architecture
of ADSL-1 CAP System ………………………………….. 6
2.1.1 The CAP Transmitter …………...…….………………… 7
2.1.2 The CAP Receiver ………….………………….………………. 8
2.2 Automatic Gain Control ………………………………….. 9
2.3 Barker-Code Mixed-Mode AGC …………………………. 13
2.4 AGC Methematical Model ……………………………….. 17
2.5 System Simulation Result and Parameter Assignment …… 18
Chapter 3 Analog Forward Path Circuit Designs ……. 21
3.1 Variable Gain Amplifier ………………………………….. 21
3.1.1 Current Squaring Circuit ………………………………………. 22
3.1.2 Main Amplifiers of the VGA …………………………………... 24
3.2 Bandpass Filter …………………………………………… 29
3.2.1 Automatic Tuning Mechanism ………………………………… 31
3.2.2 Band-Pass Filter ………………………………………………... 33
3.3 Gain & Buffer …………………………………………….. 39
3.4 Complete Forward Path …………………………………... 41
Chapter 4 Feedback Path Circuit Designs ……………. 43
4.1 Barker Code Detector …………………………………….. 43
4.2 Digital/Analog Converter ………………………………… 46
4.3 Integrator ………………………………………………….. 48
4.4 Closed Loop Simulation ………………………………… 49
Chapter 5 VLSI Implementation ……………………… 51
5.1 Layout Design …………………………………………….. 51
5.2 Post-Layout Simulation …………………………………... 51
5.2.1 Macro …………………………………………………………... 53
5.2.2 Open Loop …………………………………………………….. 57
5.2.3 Closed Loop ……………………………………………………. 58
Chapter 6 Conclusions …………………………………. 59
Appendix A. Pin Assignment ………………………… 61
Appendix B. Testing strategy ………………………….. 64

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[2] Muh-Tain Shiue "AGC, Initial Acquision and Timing Recovery Techniques for Qam ADSL Transceiver", APCC Proceedings, August 1993.
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[4] C. M. Lin, "Automatic Gain Control VLSI Architecture for ADSL-1 CAP System", Master's thesis, Department of Electrical Engineering, National Central Univ., Taiwan, R.O.C., Sep. 1994.
[5] Remco J.Wiegerink, "A CMOS Four-Quadrant Analog Current Multiplier", ISCAS, 1991.
[6] Remco J.Wiegerink, "A CMOS Wideband Linear Current Attenuator with electronically Variable Gain", ISCAS, 1993.
[7] James Hong, "VLSI Analog Filter", Master's Thesis, Department of Electrical Engineering National Central University, Chung-Li, Taiwan, Republic of China, Sept. 1993.
[8] Ivan Riis Nielsen, "A Novel SFG Structure for C-T High-Pass Filters", IEEE JSSC, vol.28, No.7, July 1993.