臺灣博碩士論文加值系統

在無線通訊系統之傳送接收機中，本地振盪源(local oscillator)扮演很重要的角色。其中此本地振盪源的設計通常是建立於鎖相迴路之系統中以確保有穩定以及精確之頻率輸出，此系統即為頻率合成器。在大部分的應用中，頻率合成器(frequency synthesizer)之相位雜訊(phase noise)主宰了整個傳送接收機之效能。而壓控振盪器(voltage-controlled oscillator)亦為頻率合成器中之ㄧ個重要電路。因此壓控振盪器的設計需要做到具有低相位雜訊、以及可以克服製程變異。此外，低功率消耗為一重要趨勢，所以找到最好的功率消耗偏壓點而達到最佳化之相位雜訊亦為壓控振盪器之設計挑戰。
本論文主要研究為頻率合成器之設計，並提出一個具有最佳化偏壓架構之電感電容式壓控振盪器(LC-VCO)。VCO輸出雜訊有相當大的成分是由偏壓於飽和區之電流源電晶體以及參考電路(Bandgap)所貢獻，於是本設計VCO採取操作於三極管區之電流源。三極管區操作因為其電晶體轉導值(transconductance，gm)較小，會有較小的閃爍雜訊(flicker noise)以及熱雜訊(thermal noise)，所以會有較少之雜訊被混頻至振盪器之輸出端。
然而，操作於三極管區之電晶體，其性質以及偏壓電流容易隨著製程變異而改變，因此本設計亦加入一混合訊號模式之自動化振幅調節器(AAC)來偵測輸出振幅並且迴授控制其偏壓狀態，使其可以做到不與製程電壓溫度變異而改變。
另外，由於射頻(RF)電路對於雜訊相當敏感，因此有較低之電壓源雜訊對於射頻電路而言是相當重要的。也因此在此最佳化偏壓振盪器設計中，為了使電路體具有更好的表現，最後在設計中便加入了一個低壓差電壓穩壓器 (low-dropout voltage regulator)來增加整體電路之PSRR (power supply rejection ratio)。
量測結果顯示此顆使用點一八深次微米金氧半製程之振盪器晶片比起傳統振盪器飽和區偏壓電流源架構擁有較佳之相位雜訊。在5.46-GHz振盪頻率之下，此振盪器在100-kHz頻率偏移下達到-103.3 dBc/Hz之相位雜訊，此時在1.8伏特之電壓供給下消耗電流5.16毫安培。
最後，此最佳化偏壓壓控振盪器技術被整合於5-GHz頻率合成器中，整顆晶片大小為1.58 x 1.226 mm2。

In wireless communication systems, the local oscillator (LO) plays an important role. The oscillator used in a RF transceiver is usually embedded in a phase-locked loop (PLL) system so as to achieve a stable and precise definition of the output frequency, and this system is called “frequency synthesizer”. The phase noise of a frequency synthesizer affects the performance of the whole transceiver. In a PLL-based frequency synthesizer, VCO noise often dominates the PLL phase noise performance. Hence, it is paramount to design a low-noise under all PVT variations.
In this work, a frequency synthesizer with optimally biased LC-VCO is proposed. For a conventional CMOS VCO design, the noise contributions from the VCO’s saturation tail current transistor and the whole reference bandgap current generation path are significant. To address this issue, a low-noise VCO biasing technique is proposed. Here, conventional tail current source transistors biased in the saturation region are replaced with a triode-region transistor current source. Triode transistors generate much less noise (both thermal and flicker noise) than the saturation devices do due to the smaller transconductance gm; hence, the up-converted noise is also reduced.
For a triode-region biasing transistor, the biasing current is sensitive to PVT variations. Thus, to achieve a PVT independent design, an automatic amplitude control (AAC) scheme is introduced. This servo-circuit detects the VCO output voltage swing to determine the optimum triode-region transistor array settings through a feedback loop. The AAC circuit is designed in a mixed-signal topology, so it is only turned on to calibrate the oscillation amplitude and biasing current when necessary. Thus, additional power consumption and noise from the AAC circuit are not concerned.
This work further incorporates a voltage regulator. For noise-sensitive circuits, it is a good practice to employ voltage regulators to ensure good noise performance in a SOC environment. Thus, a low-dropout (LDO) voltage regulator is integrated to provide the VCO supply voltage and increase the circuit PSRR.
Fabricated in a 0.18-μm CMOS process, the measurement results show the proposed topology achieves a lower phase noise than the conventional saturation-biased current source does. At 5.46 GHz, the VCO system demonstrates a phase noise of -103.3 dBc/Hz at 100-kHz offset, while dissipates 5.16 mA from a 1.8-V supply. This corresponds to an FOM of 188.3 dBc/Hz/mW.
Finally, these proposed techniques are incorporated into a 5-GHz PLL design. The whole circuits occupy an area of 1.58 x 1.226 mm2.

1. Introduction……………………………………………………………… 01
1.1 Motivation ………………………………………………………… 01
1.1.1 Triode Region Biasing LC-VCO…………………………… 01
1.1.2 Automatic Amplitude Control ……………………………… 02
1.1.3 Embedded Low-Dropout Voltage Regulator………………… 02
1.2 Thesis Organization……………………………………………….. 03

2. Introduction of Frequency Synthesizers……………………………… 05
2.1 Introduction………………………………………………………… 05
2.2 Frequency Synthesis Techniques………………………………….. 06
2.2.1 Integer-N Frequency Synthesizer…………………………… 06
2.2.2 Fractional-N Frequency Synthesizer………………………… 07
2.2.3 DLL-Based Frequency Synthesizer………………………… 08
2.2.4 Direct Digital Frequency Synthesizer………………………. 09

3. An Optimally Biased LC-VCO……………………………………….. 11
3.1 Introduction………………………………………………………... 11
3.2 LC-VCO with Triode-Region Transistors Current Source………… 12
3.3 Automatic Amplitude Control (AAC) System Architecture………. 15
3.3.1 Why AAC Loop?.................................................................... 16
3.3.2 Proposed Mixed-Signal AAC Architecture…………………. 16
3.3.3 AAC Building Block Design……………………………….. 18
3.3.3.1 Amplitude Peak Detector and LPF……………………. 18
3.3.3.2 Digital Calibration Circuits……………………………. 19
3.3.3.3 Comparator……………………………………………. 21
3.4 LDO Voltage Regulator Design…………………………………… 21
3.4.1 Conventional LDO Voltage Regulator……………………… 22
3.4.2 The Adopted LDO Voltage Regulator………………………. 24
3.4.2.1 The Concept of Internal Zero Compensation………….. 24
3.4.2.2 Design Considerations for The VCCS………………… 25
3.4.2.3 Pass Transistor and Error Amplifier…………………… 27
3.5 Simulation ………………………………………………………… 28
3.5.1 System Simulation………………………………………….. 28
3.5.2 VCO Phase Noise Simulation ……………………………… 29
3.5.3 AAC Loop Simulation……………………………………… 29
3.5.4 LDO Voltage Regulator Simulation………………………… 30

4. A 5-GHz Frequency Synthesizer Implementation……………………… 37
4.1 Introduction………………………………………………………… 37
4.2 PLL System Behavior Simulation and Noise Analysis……………. 38
4.2.1 System Noise Analysis……………………………………… 38
4.2.2 PLL System Behavior Simulation and Parameter Selections.. 43
4.3 PLL Building Block Design……………………………………….. 52
4.3.1 VCO and Buffers…………………………………………… 52
4.3.2 Retimed Divider…………………………………………….. 55
4.3.3 PFD and Charge Pump……………………………………… 58
4.3.4 Low-Pass Filter……………………………………………… 61

5. Measurement Results…………………………………………………… 63
5.1 Testing Setup………………………………………………………. 63
5.2 Printed Circuit Board Design……..……………………………….. 64
5.2.1 Chip Pin Configurations and PCB Diagram………………… 64
5.2.2 Power Supply Generator …………………………………… 67
5.2.3 Voltage Reference Generator……………………………….. 68
5.3 Experimental Results……………………………………………… 69
5.3.1 LC-VCO…………………………………………………….. 69
5.3.2 AAC Loop…………………………………………………… 74
5.3.3 Voltage Regulator…………………………………………… 75

6. Conclusions & Future Works…………………………………………… 79
6.1 Conclusions………………………………………………………… 79
6.2 Future Works………………………………………………………. 80

References………………………………………………………………….. 81

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