臺灣博碩士論文加值系統

　　本文討論在無雜訊幹擾的情況下，第一階和第二階鎖相迴路在頻率和相位有步態跳動時的暫態反應。經由此暫態反應的研究，我們可得知(1)當鎖相迴路在鎖住的狀況下，甚麼條件可使鎖相迴路繼續鎖住？(2)如何選取適當的鎖相迴路結構及參數，使暫態反應時間較短？首先，我們介紹鎖相迴路的基本原理和各基本功能方塊。接著作線性模式的分析，分別求出不同結構鎖相迴路的暫態反應公式和其鎖住範圍。最後再以一組實際線路所得結果來作一驗證。

This thesis discusses the frequency step response and the phase step response of first-order and second-order phase-locked loops under no noise condition. With these studies, we may understand (1)If the PLL is initially locked, under what conditions will the PLL remain locked? (2)How to choose the PLL parameters to minimize the transient time? First, we introduce the basic principles and basic functional blocks of PLL. Second, we make a linear mode analysis of the various configurations of PLL, then to solve their formulas of the frequency step response and the phase step response, and to find their lock ranges respectively. Finally, we present a realized circuit of PLL and compare the results of this circuit with the formulas above.