臺灣博碩士論文加值系統

在可攜式商品中，隨著功能的增加及工作速度的提昇，其所消耗的電量也跟著大幅上升，因此提高待機時間將是一個很重要的需求。快取記憶體消耗了處理器中大部分的電力，因此我們將提出一個新的快取記憶體架構，以減少快取記憶體所消耗的電力。
在這裡我們將提出兩個主題，一個是分割字典的程式碼壓縮方式(code compression)，這個壓縮方法是使用兩個字典分別對快取記憶體及主記憶體作壓縮，以求能夠同時達到省電及縮減程式碼的目的。另一個是使用位址轉換(Address Translation)的低耗電之壓縮快取記憶體架構。我們所要提出的低耗電快取記憶體架構是以一個位址轉換器取代標籤陣列( Tag Array )，以降低快取記憶體命中(Cache Hit)時的電力消耗，並減少快取記憶體未命中(Cache Miss)時的電力消耗；另外，為了提高快取記憶體的命中率(Cache Hit Ratio)，我們結合了一個以字典式壓縮法為基礎的壓縮方法以提高快取記憶體中指令的密度及命中率，並且最小化指令解壓縮時所消耗的電力。
除此之外，由於我們所提出的架構及壓縮方法的特性，我們也使用位址轉換器來重複利用已經被複製到快取記憶體中的指令區塊在主記憶體的空間，以減少所需的主記憶體空間。
實驗結果顯示，我們所提出的快取記憶體架構確實能有效的節省電力消耗，另外主記憶體的大小也可以節省快取記憶體大小的空間。

In portable products, with more and more increasing functions and
work speed, the power dissipation is more and more plenty. Cache
consumes the greater part of power dissipation in processor, so
we will present a new low power cache architecture to reduce
power dissipation in cache.
We present two subjects in this paper. One is that separate
dictionary code compression. This compression scheme is that uses
two dictionaries to compressed cache and memory instructions
individually in order to reduce power dissipation and obtain good
compression ratio. Another is low power cache architecture that
uses address translation and combines code compression. Our low
power cache architecture is to replace the tag array with an
address translation. This architecture can reduce power
dissipation for cache hit and cache miss. In addition, we combine
a compression method that is dictionary based compression scheme
with our low power cache architecture. The compression method can
increase the code density and cache hit ratio, and the power of
instruction decompression is minimized.
Furthermore, the instructions in cache are duplicated for memory.
If the instruction is in cache, the processor will not access the
main memory. As a result of characteristic of our cache
architecture and compression method, we can further compact the
instruction space in memory with Address Translator for reducing
main memory size.
Moreover, since the instructions in the cache are duplicated form
memory, we may further compact the instruction space in the
memory by eliminating these duplicate instructions via additional
address translation.
The experimental results show that this cache architecture can
efficiently reduce power dissipation and main memory size can be
reduced cache size.

1 Introduction
1.1 Motivation
1.2 Main Contribution
1.3 Thesis Organization
2 Background and Related work
2.1 Overview
2.2 Low Power Architecture
2.3 Code Compression
3 Separate Dictionary for Cache and Memory
3.1 Motivation
3.2 Compression Caching Frequently-Executed Instructions
3.3 Frequently-Used Instructions Compression
3.3.1 Encoding Top N Instructions for Memory Compression
3.3.2 Exploiting Compression Method for Top N Frequently-Used Instructions
4 Reducing Tag Array with Application-Specific Address Translation
4.1 Motivation
4.2 Organization of Application-Specific Compressed Cache
4.3 Using Address Translation for Reducing Memory Size
5 Performance Evaluation
5.1 Experiment Environment
5.2 Simulation Results
6 Conclusion

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