臺灣博碩士論文加值系統

H.264/AVC 是針對影像編碼最新的技術，傳統數位訊號處理器無法有效率的處理這個新編碼技術。最主要的原因是因為 H.264 需要大量而且複雜的運算。而現有數位訊號處理器的指令集無法做有效率的運算。我們需要藉由加速 H.264 最常使用的運算函式來提升整體的效能。研究的結果顯示，內插法這個功能站去 H.264 解碼器 22% 的時間，而他的主要功能，是去預測畫素在畫面移動之後會變成什麼顏色。藉由這個功能，H.264 提供了更高的壓縮比，卻能同時提供相同的影像品質。本篇論文中，我們著重在內插法，設計新的指令集，以加速內插法運算的速度。以 Starfish 數位訊號處理器的架構為基礎，針對內插法設計出新指令。藉由加入非常小額外負擔的硬體，並盡量運用原有的硬體資源，創造出新的資料處理路徑，而更快速的去完成內插法的運算。為了能控制新的運算，我們也針對新的指令作出對應編碼，硬體架構修改完成的同時，軟體部分也要提供相對應的支援。我們修改了組譯器以及模擬器，將其加入新指令的組語以及對應的編碼。為了能更精確的確認實驗結果，我們也將內插法函式使用原本的指令集來撰寫，以求得原本更最佳化的對照組。實驗結果顯示，我們定義的指令集可以改善內插法將近45%。

H.264/AVC is the state-of-the-art video coding standard. One of the basic implementation issues of H.264 standard isthat its computational complexity is very high. By the profiling result, we focus on the interpolation procedure which consumes up to 22% of the execution time. In this thesis, we propose a number of new instructions for interpolation and hardware architecture to support these new instructions. The experimental result shows that by these new instructions, computation time is reduced 30% in average.

Contents
1 Introduction 1
2 Interpolation Algorithm and New Instructions 4
2.1 The Interpolation Procedure . . . . . . . . . . . . . 4
2.1.1 Motion Vectors . . . . . . . . . . . . . . . . . . 4
2.1.2 Generation of Interpolated Samples . . . . . . . . . 5
2.1.3 Algorithm Flow . . . . . . . . . . . . . . . . . . . 7
2.2 New Instructions . . . . . . . . . . . . . . . . . . . 9
2.2.1 CHKB instruction . . . . . . . . . . . . . . . . . 12
2.2.2 BFLOAD instruction and LDMVBF instruction . . . . . 13
3 Architecture and Software . . . . . . . . . . . . . . .19
3.1 The Architecture of Starfish. . . . . . . . . . . . . 19
3.1.1 Parallel Issue . . . . . . . . . . . . . . . . . . 19
3.1.2 Pipeline Issue . . . . . . . . . . . . . . . . . . 19
3.2 Data Path for New Instructions . . . . . . . . . . . 21
3.2.1 Hardware Design for CHKB instruction . . . . . . . 21
3.2.2 Hardware Design for BFLOAD and LDMVBF Instructions .23
3.3 Encoding of New Instructions. . . . . . . . . . . . . 24
3.4 Tool-Chain of Starfish. . . . . . . . . . . . . . . . 25
4 Experimental Results 29
4.1 Software Performance. . . . . . . . . . . . . . . . . 29
4.2 Hardware Overhead . . . . . . . . . . . . . . . . . . 30
5 Conclusions. . . . . . . . . . . . . . . . . . . . . . .32

[1] ISO/IEC 14496-10, ITU-T Rec. H.264, Joint Video Specification, October 2002.
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pp.2136-2139, Vol.3, 2005
[8] P.P. Dang, "An Efficient VLSI Architecture for H.264 Subpixel Interpolation Coprocessor", ICCE'06, pp. 87-88, 2006