臺灣博碩士論文加值系統

動態影像編碼系統中，區塊比對演算法佔有著重要的地位，因為它對於消除視訊編碼系統中時間上的冗餘性，是一個最簡單且有效的方法。本論文採用一個有效率的硬體架構來實現全域搜尋H.264可變區塊區塊比對法，此架構最主要的優點是有最低的計算延遲與高度的計算吞吐量，此硬體電路經由驗證模擬，並將H.264可變區塊區塊比對電路經過最佳化處理後並合成於Xilinx公司所推出的FPGA開發版，本論文採用四種Xilinx所推出的FPGA開發板及晶片型號，選出最適合本硬體架構的晶片，快速開發可變區塊區塊比對電路的雛形。

The block occupies is important position than to the algorithm of performing in the code system of the dynamic image. Because it, for dispelling the redundancy on time in the code system of video-information, it is a simplest and effective method. Thesis this adopt one efficient hardware structure to accomplish H.264 variable block matching. This hardware circuit by way of the prove simulation, and H.264 variable block than practical operation of the Xilinx FPGA. This text adopts FPGA that three kinds of Xilinx introduce and develops the board and chip type, elect the chip most suitable for the structure of a hardware, develop the mode of variable block circuit.

目錄
中文摘要∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ i
英文摘要 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ ii
致謝∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ iii
目錄∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ iv
表目錄∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ v
圖目錄∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ vi
符號說明∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ vii
第一章 緒論∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 1
1.1文獻回顧∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 1
1.2 研究動機與目的∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 4
1.3 研究方法與步驟∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 6
1.4 章節安排∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 7
第二章 基本理論介紹∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 8
2.1 H.264視訊壓縮標準∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 8
2.2 動態影像編碼系統 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 9
2.3 移動估測∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 12
2.4 區塊比對法則∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 14
2.5 全域搜尋區塊比對法則∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 16
2.6 絕對誤差總和∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 18
2.7 H.264可變區塊區塊比對法∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 19
第三章 H.264可變區塊區塊比對硬體架構∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21
3.1 移動估測單元∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21
3.2 絕對誤差總和模組∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 22
3.3 可變區塊移動估測處理器∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 32
第四章 H.264可變區塊區塊比對法硬體開發環境∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 35
4.1 硬體開發環境介紹∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 35
4.2 專案建置∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 37
4.3 Function Simulation的執行∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 38
第五章 模擬結果與結論∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 39
5.1 模擬結果∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 39
5.2 效能分析∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 45
5.3 結論∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 48
參考文獻∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 49
附錄∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 51
簡歷∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 54

1.Zhongli He, Ming L. Liou, Philip.C.H. Chan, and R. Li, “An Efficient VLSI Architecture for New Three-step Search Algorithm,” Proceeding of the 38th IEEE Midwest symposium on Circuits and Systems, Vol.2, pp.1228-1231, 1996.
2.Wen-Jyi Hwang, Chien-Min Ou, Wen-Ming Lu, and Chun-Fu Lin, “VLSI Architecture for Motion Vector Quantization,” IEEE Trans. Consumer Electronics, vol. 49, no. 1,pp. 237-242, 2003.
3.“Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to About 1.5 Mbit/s: Video,” ISO/IEC 11172-2, 1993.
4.“Generic Coding of Moving Pictures and Assoicated Audio Information: Video,” ISO/IEC 13818-2-ITUT-T Rec. H.262, 1995.
5.Reoxiang Li, Bing Zeng, Liou, and M. L., “A new three-step search algorithm for block motion estimation,” IEEE Transactions on Circuit and System for Video Technology, Vol. 4, No. 4, pp.438-442, August 1994.
6.Yeong-Kang Lai, Yeong-Lin Lai, Yuan-Chen Liu, Po-Cheng Wu and Liang-Gee Chen, Senior Member, “VLSI Implementation of the Motion Estimator with Two-Dimensional Data-Reuse,” IEEE Transactions. Consumer Electronics, Vol. 44, pp.623-629, 1998.
7.Yoon-Yung Lee and John W. Woods, “Motion Vector Quantization for Video Coding,” IEEE Trans. Image processing, Vol. 4, No. 3, 1995.
8.Chien-Min Ou, Chain-Feng Le and Wen-Jyi Hwang, “An Efficient VLSI architecture for H.264 Variable Block Size Motion Estimation,” IEEE Transactions on Consumer Electronics, Vol. 51, No. 4, pp.1291-1299, Nov. 2005.
9.Lai-Man Po and Wing-Chung Ma, “A novel Four-Step Search Algorithm for Block Motion Estimation,” IEEE Transactions on Circuit and Systems for Video Technology, Vol. 6, No. 3, pp.313-317, June 1996.
10.Peter Pirsch, “VLSI Architectures for Video Compression-A Survey,” Proc. IEEE, Vol.83, pp.220-246, 1995.
11.Kamisetty Ramamohan Rao and J. J. Hwang, Techniques and Standards for Image, Video and Audio Coding, Prentice Hall, 1996.
12.Jun-Fu Shen, Tu-Chih Wang and Liang-Gee Chen, “A novel low-power full-search block-matching motion-estimation design for H.263+,” IEEE Trans. Circuits and Systems for Video Technology, pp.890-897, 2001.
13.CCITT SGXV, “Description of reference model 8 (RM8)”, Working Party XV/4, Specialists Group on Coding for Visual Telephony, Doc.525, June 1989.
14.Luc-de Vos and Matthias Schobinger, “VLSI architecture for a flexible block matching processor,” IEEE Trans. Circuits and Systems for Video Technology, Vol.5, pp.417-428, 1995.
15.John Wiley and Sons, H.264 and MPEG-4 Video Compression, I.E.G. Richardson, 2003.
16.Swee-Yeow Yap and John-V. McCanny, “A VLSI Architecture for Variable Block Size Video Motion Estimation,” IEEE Trans. Circuits and Systems, pp.384-389, Vol. 51,2004.
17.Shan-Zhu and Kai-Kuang Ma, “A new diamond search algorithm for fast block-matching motion estimation,” Int. Conf. Information, Communications and Signal Processing (ICIS), Vol. 1, Setp.9-12, pp.292-296, 1997.
18.Virtex-4 MB Development Board User’s Guide, 2005.