臺灣博碩士論文加值系統

本篇論文討論以Manchester進位鏈為基礎架構的加法器。以動態、pass-transistors為基礎的Manchester進位鏈加法器、有最少的電晶體數，若可以找到快速並容易使用的越級（bypass）方法，則此架構將可以用最少的電晶體數來製成多位元的高速加法器。在本文中我們提出新的越級（bypass）方法、輸出緩衝級（buffer）和進位鏈上的緩衝級（buffer）的使用方式，最後並組成一個64位元的加法器。
本文中之數據均以台灣積體電路公司的0.6μm SPDM CMOS 的製程參數以HSPICE模擬而來。

This thesis discusses the adder based on Manchester carry chain. The Manchester carry chain circuit based on pass-transistors and dynamic logic techniques have the smallest transistor count among all carry look-ahead circuits including domino and other static techniques. We introduce new bypass circuit、new output buffer and carry-chain buffer. Then we design a 64-b adder based on the circuits introduced on the thesis.
The analysis data based on TSMC 0.6μm SPDM CMOS technology got by HSPICE.

中文摘要 iii
英文摘要 iv
誌謝 v
圖目錄 viii
1緒論 1
1.1 研究動機 ………………………………………………………………1
1.2 Manchester Carry Chain ……………………………………………1
1.3 論文組織 ………………………………………………………………4
2 輸出緩衝級 5
2.1 簡介 ………………………………………………………………5
2.2 Pre-charge & Pre-charge 電路 ………………………………6
2.3 Pre-charge & Pre-charge 電路之輸出 buffer電容分析 10
2.4 結論 ………………………………………………… …………11
3 傳輸閘 12
3.1 簡介 ………………………………………………………………12
3.2 傳輸閘的使用 ……………………………………………………12
3.3 Bypass 訊號的取出與加入的方 ………………………………15
3.4 進位鏈(Carry Chain)上緩衝級（buffer）的設計 ……… …27
3.5 結論 ………………………………………………………………35
4 全加器 36
4.1 簡介 ………………………………………………………………36
4.2 進位產生器 ………………………………………………………36
4.3 其它電路 …………………………………………………………42
4.4 全加器 ……………………………………………………………43
4.5 結論 ………………………………………………………………44
5 結論 46
參考文獻 48
自傳 50

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