臺灣博碩士論文加值系統

本論文包含兩個主題：具有低溫度敏感性與抗製程飄移的動態隨機存取記憶體與無ESR電阻補償之低壓降高精準度線性穩壓器。
第一個主題探討動態隨機存取記憶體的更新週期，以1P8M 0.13-μm CMOS製程來實現一個4-Kb的動態隨機存取記憶體實現。本論文提出使用一適應性震盪器(adaptive oscillator)，其產生的更新週期會根據溫度和製程漂移而自動調整改變，當溫度升高時更新週期變短；反之，溫度降低時，更新週期則變長，以確保資料的正確。其更新週期為動態表現的，用以減少不必要的更新執行次數與功率的消耗。
第二個主題為探討直流電壓降壓器，提出一個不需外接ESR電阻補償的低壓降線性穩壓器，以2P4M 0.35-μm CMOS製程實現。經由內部的頻率補償，晶片量測結果可承受最大負載電流為240 mA，線性調節率與負載調節率誤差皆小於3 %。

The thesis is composed of two topics: a power-saving DRAMs with an adaptive refreshing clock generator, and a high precision low dropout regulator with nested feedback loops.
In the first topic, an adaptive refreshing circuitry design for DRAMs is presented in this work.
The proposed refreshing circuitry utilizes a voltage comparator to monitor the voltage drop caused by
the data loss of a memory cell resulted from leakage currents to dynamically adjust the refreshing
period of DRAM cells. A process variation monitor is also included in the proposed design to
compensate the process drifting problem. Therefore, the proposed design is insensitive to temperature
variations as well as process drifts. The period of the refreshing clock is automatically adjusted to save
a great portion of standby power of DRAMs. A 4-Kb DRAM is implemented using a typical 0.13-μm
1P8M digital CMOS process. Post-layout simulation results and a prototype on silicon justify the
correctness of the adaptive refreshing cycles generated by the proposed design.
In the second topic, a high precision low dropout regulator (LDO) with nested feedback loops is
proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback
loop comprising an Error Amplifier, the independence of off-chip capacitor and ESR is ensured for
different load currents and operating voltages. Therefore, in low Iddq or low voltage scenarios, the total error of the output voltage caused by line and load variations is less than ±3% according to the
on-silicon measurement results.

致謝 ............................................................................................................. i
摘要 ............................................................................................................ ii
Abstract .................................................................................................... iii
目錄 ........................................................................................................... iv
圖目錄 ..................................................................................................... viii
表目錄 ....................................................................................................... xi
第一章 概論 ........................................................................................... 1
1.1 前言 .............................................................................................. 1
1.2 相關文獻與研究探討 .................................................................. 3
1.2.1 動態隨機存取記憶體更新電路 ...................................... 3
1.2.2 低壓降線性穩壓器 .......................................................... 4
1.3 研究動機 ...................................................................................... 6
1.4 論文大綱 ...................................................................................... 7
第二章 具有低溫度敏感性與抗製成飄移的動態隨機存取記憶體 ... 8
2.1 簡介 .............................................................................................. 8
2.2 電路架構 ...................................................................................... 8
2.3 電路設計 ...................................................................................... 9
2.3.1 記憶單元 ...................................................................... 12
2.3.2 電壓比較器 ................................................................... 13
2.3.3 參考電壓源 ................................................................... 14
2.3.4 控制訊號產生器 ........................................................... 15
2.3.5 感測放大器 ................................................................... 17
2.4 預計規格 .................................................................................... 19
2.4.1 效能比較 ....................................................................... 19
2.5 晶片佈局 .................................................................................... 20
2.5.1 佈局考量 ....................................................................... 20
2.5.2 佈局平面圖 ................................................................... 21
2.6 電路模擬與晶片量測 ................................................................ 21
2.6.1 電路模擬結果 ............................................................... 21
2.6.2 晶片實作與量測結果 ................................................... 24
2.7 晶片實作之討論 ........................................................................ 26
第三章 無ESR 電阻補償之低壓降高精準度線性穩壓器 ............... 27
3.1 簡介 ............................................................................................ 27
3.2 低壓降線性穩壓器之重要參數 ................................................ 27
3.2.1 輸出電壓差 (Dropout voltage) .................................... 28
3.2.2 線性調節率 (Line Regulation) .................................... 29
3.2.3 負載調節率 (Load Regulation) ................................... 29
3.2.4 接地電流 (Ground Current) ......................................... 30
3.2.5 電源效率 (Efficiency) .................................................. 30
3.2.6 暫態響應 (Transient response) .................................... 31
3.2.7 頻率響應 (Frequency response) .................................. 31
3.3 電路架構 .................................................................................... 35
3.4 電路設計 .................................................................................... 36
3.4.1 參考電壓源 ................................................................... 36
3.4.2 誤差放大器 ................................................................... 40
3.4.3 輸出功率電晶體 ........................................................... 41
3.4.4 源極隨偶器 ................................................................... 42
3.4.5 頻率補償 ....................................................................... 43
3.5 預計規格 .................................................................................... 45
3.6 晶片佈局 .................................................................................... 45
3.6.1 佈局考量 ....................................................................... 45
3.7 電路模擬與晶片量測 ................................................................ 46
3.7.1 電路模擬結果 ............................................................... 46
3.7.2 晶片實作與量測結果 ................................................... 53
3.7.3 效能比較 ....................................................................... 56
3.8 晶片實作量測之討論 ................................................................ 57
第四章 結論及成果 ............................................................................. 58
參考文獻 ................................................................................................... 60
圖目錄
圖1.1.1 直流轉壓示意圖 ....................................................................... 2
圖1.2.1 不同角落下的漏電情形 ........................................................... 4
圖1.2.2 傳統LDO 電路架構圖 ............................................................. 5
圖2.2.1 系統架構圖 ............................................................................... 9
圖2.3.1 適應性振盪器架構圖 ............................................................. 11
圖2.3.2 記憶單元 ................................................................................. 13
圖2.3.3 電壓比較器 ............................................................................. 14
圖2.3.4 參考電壓源 ............................................................................. 15
圖2.3.5 控制訊號產生器 ..................................................................... 16
圖2.3.6 上升邊緣偵測器 ..................................................................... 17
圖2.3.7 延遲模組 ................................................................................. 17
圖2.3.8 感測放大器 ............................................................................. 18
圖2.5.1 晶片佈局平面圖 ..................................................................... 21
圖2.6.1 適應性振盪器模擬 ................................................................. 22
圖2.6.2 不同角落下的更新週期 ......................................................... 23
圖2.6.3 讀、寫、更新的內部訊號模擬 ............................................. 23
圖2.6.4 晶片照相圖 ............................................................................. 24
圖3.2.1 PMOS 壓降範圍 ..................................................................... 29
圖3.2.3 接地電流 ................................................................................. 30
圖3.2.4 線性穩壓器交流模型 ............................................................. 32
圖3.2.5 線性穩壓器頻率響應 ............................................................. 35
圖3.3.1 系統架構圖 ............................................................................. 36
圖3.4.1 參考電壓源 ............................................................................. 39
圖3.4.2 誤差放大器 ............................................................................. 41
圖3.4.3 源極隨偶器 ............................................................................. 42
圖3.6.1 佈局平面圖 ............................................................................. 46
圖3.7.1 參考電壓源對溫度變化模擬結果 ......................................... 47
圖3.7.2 參考電壓源對輸入電壓變化模擬結果 ................................. 47
圖3.7.3 誤差放大器在Vin=5 V 時模擬結果 ...................................... 49
圖3.7.4 誤差放大器在Vin=3.45 V 時模擬結果 ................................. 49
圖3.7.5 線性調節率模擬結果 ............................................................. 50
圖3.7.6 負載調節率模擬結果 ............................................................. 51
圖3.7.7 輸出電壓差模擬結果 ............................................................. 51
圖3.7.8 PSRR 在Vin=5 V 時模擬結果 ................................................ 52
圖3.7.9 PSRR 在Vin=3.45 V 時模擬結果 .......................................... 52
圖3.7.10 晶片照相圖 ........................................................................... 53
圖3.7.11 輸出電壓差量測結果 ........................................................... 54
圖3.7.12 線性調節率量測結果 ........................................................... 54
圖3.7.13 線性調節率穩定時間 ........................................................... 54
圖3.7.14 負載調節率量測結果 ........................................................... 55
圖3.7.15 負載調節率穩定時間 ........................................................... 55
圖3.7.16 3.08 KHz 時PSRR 量測 ....................................................... 55
圖3.7.17 30.8 KHz 時PSRR 量測 ....................................................... 55
表目錄
表1.3.1 動態週期與傳統固定更新週期功率比較表 ........................... 6
表2.3.1 系統內部所需電壓 ................................................................. 15
表2.4.1 FF 角落下不同溫度的更新週期 ............................................ 19
表2.4.2 FF 角落下不同溫度的功率消耗 ............................................ 19
表2.4.3 適應性震盪器所占面積比例 ................................................. 19
表2.4.4 適應性震盪器在1-Mb DRAM 所占面積比較 ..................... 19
表2.4.5 效能比較 ................................................................................. 20
表2.6.1 參考電壓源對VDD 飄移的量測結果 ................................... 25
表2.6.2 參考電壓源對溫度飄移的量測結果 ..................................... 25
表3.2.1 功率電晶體比較 ..................................................................... 41
表3.5.1 預計規格列表 .......................................................................... 45
表3.7.1 誤差放大器在Vin=5 V 時的頻率響應 .................................. 48
表3.7.2 誤差放大器在Vin=3.45 V 時的頻率響應 ............................. 48
表3.7.3 量測結果 ................................................................................. 55
表3.7.4 本設計與其他低壓降線性穩壓器比較 ................................. 56
表4.1.1 晶片下線記錄 ......................................................................... 59

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