臺灣博碩士論文加值系統

多核心處理器被廣泛用於手持式裝置、筆記型電腦與伺服器等應用，其中動態電壓調變與可適應性電壓調變等技術經常被用於降低處理器核心之電源功耗及提升處理器系統的散熱性能。此外，對每一核心獨立做動態與可適應性電壓調變可以使處理器的能量使用效率最大化。不過，當處理器中的核心增加時，使用片外切換式電壓轉換器來實現動態電壓與可適應性電壓調變等技術會顯得不符合成本並且無法達到快速且有效率的電壓調變。因此，全積體化的數位線性穩壓器被提出來並用於每一核心獨立的動態與可適應電壓調變。相比於其他類型的全積體化穩壓器，全積體化數位線性穩壓器可以達到快速且最有效率及最合乎成本的動態與可適應性電壓調變控制。然而，相比於類比線性穩壓器，數位線性穩壓器在穩態時會有電流量化誤差之現象，此現象會造成輸出端出現非期望的輸出電壓漣波。而此電流量化誤差會受製成、電壓與溫度之飄移的影響，進而影響輸出電壓漣波之大小。近年來，一些文獻致力於解決上述這些問題，這些文獻中所提出的技術雖然可以消除電流量化誤差而使輸出電壓漣波被消除，但是在輸出電壓漣波與負載調節上會存在著折中的設計，而這兩項因素都會使處理器性能降低。故本篇論文提出一用於多核心處理器且具有抗製成、電壓與溫度之飄移技術的數位線性穩壓器。所提出之技術可以使電流量化誤差在任何製成、電壓與溫度之飄移下最小化並且同時維持高負載調節之性能。

Multi-core processor have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. To maximize the energy efficiency of a processor when using DVS and AVS, it is highly desirable to independently control the supply and the clock frequency for each core. As the number of cores grows, fast, cost-effective, and energy-efficient DVS and AVS schemes become prohibitively challenging to implement using off-chip switching regulators. Therefore, the fully integrated digital low-dropout regulators (DLDO) are used to achieve fast, cost-effective, and energy-efficient DVS and AVS schemes. However, the DLDO regulator has current quantization error (CQE) which produces an undesirable output voltage ripple. Moreover, the CQE of DLDO regulator is affected by process, voltage and temperature (PVT) variations, which represents the output voltage ripple of DLDO regulator depends on PVT variations. Recently, some techniques are proposed to remove CQE and thus reduce the output voltage ripple. Unfortunately, there always is a tradeoff between output voltage ripple and load regulation, which both degrade the performance of processor. As a result, the DLDO regulator with anti-PVT-variation technique is proposed in this thesis for resolve the aforementioned issues and this technique can minimize the CQE under any PVT variations and maintain good load regulation simultaneously.

摘 要 i
ABSTRACT ii
誌 謝 iii
Contents iv
Figure Captions vi
Table Captions viii
Chapter 1 Introduction 1
1.1 Background of Power Management in Multi-Core Processor 1
1.1.1 Dynamic Voltage and Frequency Scaling (DVFS) Technique 2
1.1.2 Adaptive Voltage Scaling (AVS) Technique 3
1.2 Fully Integrated Voltage Regulator 5
1.2.1 Switching Regulator 6
1.2.2 Switching Capacitor Regulator 8
1.2.3 Linear Regulator 9
1.3 Fully Integrated Digital Low-Dropout (DLDO) Voltage Regulator 11
1.4 Thesis Organization 14
Chapter 2 Prior Arts and Design 15
2.1 Output Voltage Ripple of the DLDO 15
2.2 Reduced Dynamic Stability Technique and Adaptive Control 17
2.3 Dead-Zone Control 19
2.4 Even-Driven PI Control 20
2.5 Coarse-Fine Dual Loop 22
2.6 Design Goals for Multi-Core Processor Applications 24
2.6.1 Process, Voltage and Temperature Variations 24
2.6.2 Reduction of PVT Effect and Improvement of Load Regulation 27
Chapter 3 Proposed Digital Low Dropout (DLDO) Regulator with Anti-PVT-Variation Technique and Transient Enhancement 29
3.1 Architecture of Proposed DLDO 29
3.2 Proposed Anti-PVT-Variation Technique 31
3.3 Digital Proportional-Integral-Derivative Controller 35
3.4 The Discrete Time Model of DLDO Regulator 37
3.5 DPID Control with Resolution and Nonlinearity Compensations 40
3.5.1 PD control 40
3.5.2 I control 43
Chapter 4 Circuit Implementations 45
4.1 Voltage to Time Converter 45
4.2 Time Amplifier 46
4.3 Vernier Delay Line Time to Digital Converter 47
4.4 Bound Setting Controller 49
Chapter 5 Experimental Results 51
5.1 Chip micrograph 51
5.2 Measured DLDO Load Transient 52
5.3 Measured DLDO DVS Operation 53
5.4 Measured DLDO Output Voltage Ripple 54
5.5 Measured DLDO Output Offset Voltage 55
5.6 Comparisons of Other DLDO Methodologies 56
Chapter 6 Conclusion and Future Work 58
6.1 Conclusion 58
6.2 Future work 58
Reference 59

[1] P. Macken, M. Degrauwe, M. V. Paemel, and H. Oguey, “A Voltage Reduction Technique for Digital Systems,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 238-239, Feb. 1990.
[2] T. Burd, T. Pering, A. Stratakos, R. Brodersen, “A Dynamic Voltage Scaled Microprocessor System,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 294–295, Feb. 2000.
[3] K. Nowka, G. Carpenter, E. Mac Donald, Hung Ngo; B. Brock, K. Ishii; T. Nguyen, J. Burns, “A 0.9 V to 1.95 V Dynamic Voltage-Scalable and Frequency-Scalable 32 b PowerPC Processor,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 340–341, Feb. 2002.
[4] M. Nakai, S. Akui; K. Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, M. Shimura, “Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 28-35, Jan. 2005.
[5] T. Simunic, L. Benini, A. Acquaviva, P. Glynn, G. de Micheli, “Dynamic Voltage Scaling and Power Management for Portable Systems,” Proc. of Design Automation Conference, pp. 524-529, Jun. 2001.
[6] A. Iyer and D. Marculescu, “Power Efficiency of Voltage Scaling in Multiple Clock, Multiple Voltage Cores,” Proc. of International Conference on Computer Aided Design, pp. 379-386, Nov. 2002.
[7] A. Naveh, E. Rotem, A. Mendelson, S. Gochman, R. Chabukswar, K. Krishnan, and A. Kumar., “Power and Thermal Management in Intel Core Duo Processor,” Intel Technology Journal, vol. 10, no 2, pp. 109-122, May 2006.
[8] H. Jung and M. Pedram, “Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction,” Proc. of International Conference on VLSI Design, pp. 415-420, Jan. 2008.
[9] R. Knauerhase, P. Brett, T. Li, B. Hohlt, and S. Hahn, “Using OS Observations to Improve Performance in Multi-core Systems,” Proc. of IEEE Micro, vol. 28, no 3, pp. 54-66, May-Jun. 2008.
[10] “Intelligent Energy Manager (IEM) Hardware Control System in the ARM1176JZF-SDevelopment Chip,” ARM, 2006.
[11] “Adaptive Voltage Scaling Technology,” Texas Instruments, 2011.
[12] “Adaptive (Dynamic) Voltage (Frequency) Scaling-Motivation and Implementation,” Texas Instruments, 2014.
[13] “PowerWise® Adaptive Voltage Scaling (AVS) for Portable Applications,” National Semiconductor, 2009.
[14] Q. Qiu and M. Pedram, “Dynamic Power Management Based n Continuous Time Markov Decision Process,” Proc. of Design Automation Conference, pp. 555-561, Jun. 1999.
[15] C. Isci, A. Buyuktosunoglu, C. Cher, P. Bose and M. Martonosi, “An Analysis of Efficient Multi-Core Power Management Policies: Maximizing Performance for a Given Power Budget,” Proc. of Int’l Symposium on Microarchitecture, pp. 347-358, Dec. 2006.
[16] G. Patounakis, Y. W. Li, K. L. Shepard, “A Fully Integrated On-Chip DC–DC Conversion and Power Management System,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 443-451, Mar. 2004.
[17] Ruzica Jevtić, Hanh-Phuc Le, Milovan Blagojević; Stevo Bailey, Krste Asanović, Elad Alon, Borivoje Nikolić, “Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors,” in IEEE Trans. Very Large Scale International Systems, vol. 23, no. 4, pp. 723-730, May. 2014.
[18] Abhishek A. Sinkar, Hamid Reza Ghasemi, Michael J. Schulte, Ulya R. Karpuzcu, Nam Sung Kim, “Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors,” in IEEE Trans. Very Large Scale International Systems, vol. 22, no. 4, pp. 747-758, Apr. 2014.
[19] Mike Wens, Michiel Steyaert, “A Fully-Integrated 0.18μm CMOS DC-DC Step-Down Converter, Using a Bondwire Spiral Inductor,” in Proc. IEEE Custom Integrated Circuits Conference, pp. 17-20, Sep. 2008.
[20] Mike Wens, Michiel Steyaertin, “A Fully-Integrated 130nm CMOS DC-DC Step-Down Converter, Regulated by a Constant On/Off-Time Control System,” in Proc. IEEE European Solid-State Circuits Conference, pp. 62–65, Sep. 2008.
[21] Michael Wens, Michiel Steyaert, “An 800mW Fully-Integrated 130nm CMOS DC-DC Step-Down Multi-Phase Converter, With On-Chip Spiral Inductors and Capacitors,” in Proc. IEEE Energy Conversion Congress and Exposition, pp. 3706–3709, Sep. 2009.
[22] Cheng Huang, Philip K. T. Mok. “A 100 MHz 82.4% Efficiency Package-Bondwire Based Four-Phase Fully-Integrated Buck Converter with Flying Capacitor for Area Reduction,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 2977-2988, Dec. 2013.
[23] Toke M. Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel Kossel, Matthias Brändli, Peter Buchmann, Pier Andrea Francese, “A 4.6W/mm2 Power Density 86% Efficiency On-Chip Switched Capacitor DC-DC,” in IEEE Applied Power Electronics Conference, pp. 692-699, Mar. 2013.
[24] Hanh-Phuc Le, Seth R. Sanders, Elad Alon, “Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters,” IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2120-2131, Sep. 2011.
[25] Jianping Guo, Ka Nang Leung, “A 6-μW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1896-1905, Sep. 2010.
[26] Ka Nang Leung, P. K. T. Mok, “A Capacitor-Free CMOS Low-Dropout Regulator with Damping-Factor-Control Frequency Compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003.
[27] Ka Nang Leung, Yuan Yen Mai, Philip K. T. Mok, “A Chip-Area Efficient Voltage Regulator for VLSI Systems,” in IEEE Trans. Very Large Scale International Systems, vol. 18, no. 12, pp. 1757-1762, Dec. 2010.
[28] Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai, “0.5-V Input Digital LDO with 98.7% Current Efficiency and 2.7-μA Quiescent Current in 65nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conference, pp. 1-4, Sep. 2010.
[29] Saad Bin Nasir, Arijit Raychowdhury, “On Limit Cycle Oscillations in Discrete-Time Digital Linear Regulators,” in IEEE Applied Power Electronics Conference, pp. 371-376, Mar. 2015.
[30] Saad Bin Nasir, Samantak Gangopadhyay, Arijit Raychowdhury, “A 0.13μm Fully Digital Low-Dropout Regulator with Adaptive Control and Reduced Dynamic Stability for Ultra-Wide Dynamic Range,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 1-3, Feb. 2015.
[31] Doyun Kim, Mingoo Seok, “Fully Integrated Low-Drop-Out Regulator Based on Event-Driven PI Control,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 148-149, Feb. 2016.
[32] Yong-Jin Lee, Min-Yong Jung, Shashank Singh, Tae-Hwang Kong, Dae-Yong Kim, Kwang-Ho Kim, Sang-Ho Kim, Jae-Jin Park, Ho-Jin Park, Gyu-Hyeong Cho, “A 200mA Digital Low-Drop-Out Regulator with Coarse-Fine Dual Loop in Mobile Application Processors,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 150-151, Feb. 2016.