臺灣博碩士論文加值系統

本論文探討數位D類音頻放大器 (class-D audio amplifier) 之系統設計與電路實現。D類音頻放大器因為可以達到極高的功率轉換效率而逐漸取代傳統的A類或AB類音頻放大器，其中數位D類音頻放大器 (又稱數位放大器) 將成為音頻放大器的設計趨勢。本論文發表一個為具有5.1聲道100瓦特方均根 (root-mean-square) 總輸出功率的單晶片數位放大器所設計之積分三角調變器 (delta-sigma modulator)、功率放大級與過電流保護。就所知此為文獻上第一個高度整合並成功地以積體電路實現之5.1聲道單晶片數位放大器。本論文同時也提出一個創新方法來增加數位放大器的線性輸出功率 (linear output power)，此方法適用於未來數位放大器的設計。
在5.1聲道數位放大器中，積分三角調變器被設計成具有低超取樣比 (over-sampling ratio) 並使用於將脈碼調變 (pulse code modulation) 訊號轉換至脈寬調變 (pulse width modulation) 訊號的電路中。本論文使用了一個改良架構的積分三角調變器來避免傳統架構所造成訊號雜訊比 (signal-to-noise ratio) 與最大穩定輸入振幅的衰減，這些改善在低超取樣比的情況下尤其明顯。在大功率放大級中，本論文提出了設計驅動電路的輸出波型具有不對稱之上升與下降斜率，此不對稱波型可以補償功率放大級輸出波型的誤差。為了保護此放大器不會因為短路或是連接不適當的負載所產生的大電流而損壞，本論文提出一個新的過電流保護電路，此過電流保護電路具有高抗電壓雜訊的能力同時也可以降低對元件誤差的敏感度。此5.1聲道單晶片放大器是使用0.35 um 1P3M 3.3/18-V C/D-MOS製程來實現，總晶片面積約為50mm2。於全幅 (full scale) 振幅輸入下使用A-加權濾波器 (A-weighted filter) 所量測到的峰值訊號雜訊比 (peak SNR) 與動態範圍 (dynamic range) 為84 dB，若使用零輸入下所得的雜訊能量 (noise power) 來計算則峰值訊號雜訊比與動態範圍為92 dB。上述兩種量測條件均被業界廣泛地使用。5個全頻帶聲道於8歐姆負載上的方均根輸出功率為13瓦X5而重低音聲道於3歐姆負載上的方均根輸出功率為35瓦。5.1聲道的總方均根輸出功率為100瓦，此時量測顯示的總諧波失真與雜訊比 (total-harmonic-distortion plus noise ratio, THD + N ratio) 小於0.3 %。此外，量測數據顯示放大器所能達到的最低THD + N比為0.045 %。此放大器最大功率轉換效率為88 % 且所使用的128腳位QFP封裝於底部具有金屬墊可以焊接至印刷電路板的地平面 (ground plane) 來提供額外的散熱路徑，所以於實際應用中並不需要外加額外的散熱片。因此，實現小體積與低成本的5.1聲道音頻擴大機不再是夢想，這是高功率、高傳真音頻擴大機設計的一大突破。
除了上述的單晶片音頻放大器實現之外，本論文同時提出一個創新的方法使得數位放大器在相同電壓與負載下可以延伸線性輸出功率範圍。所提出的方法可以節省電源模組的成本並且適用於未來的數位放大器設計中。對於數位放大器而言，線性輸出功率通常受限於積分三角調變器。在傳統的單級高階積分三角調變器中，因為有一部份的根軌跡 (root loci) 會跑出單位圓 (unit circle) 所以最大穩定輸入振幅受到限制。本論文提出一個新的設計方法來設計單級高階積分三角調變器使其根軌跡均位於單位圓之內且在全幅輸入下仍然可以維持高訊號雜訊與失真比 (signal-to-noise distortion ratio, SNDR)。為了達到延伸數位放大器線性輸出功率範圍的設計目標，一個由所提出的方法所設計之具有全幅穩定輸入範圍的積分三角調變器與一個傳統具有優異訊號雜訊與失真比的積分三角調變器被結合起來並應用到數位放大器中，實現結合兩個積分三角調變器的方法也同時在本論文中被提出來。跟使用傳統積分三角調變器的數位放大器相比較，所提出的技術可以增加20 % 的線性輸出功率。跟目前已發表最好的D類放大器比較，本論文所提出的技術可以延伸160 % 的極低失真輸出功率範圍。

The system design and circuit implementation of digital-input class-D audio amplifiers (digital amplifiers) are presented in this dissertation. Due to the high power efficiency of class-D amplifiers, conventional class-A and class-AB amplifiers are gradually being replaced. Digital amplifiers that can achieve high power efficiency and can directly amplify digital audio signals will eventually become the design trend of audio amplifiers. In this dissertation, the design of delta-sigma modulators (DSMs), power MOSFET drivers, and the over-current protection for a 5.1-channel single-chip digital amplifier with 100W root-mean-square (RMS) total output power is presented. To the best of our knowledge, it is the first highly integrated 5.1-channel single-chip digital amplifier. In addition, this dissertation proposes a novel DSM design method to increase the linear output power for future digital amplifier designs.
In the 5.1-channel digital amplifier, DSMs with a low over-sampling ratio (OSR) are used in circuits that convert pulse-code-modulation signals into pulse-width-modulation signals. A modified DSM structure is adopted to avoid the degradation of signal-to-noise ratio (SNR) and the maximum stable input magnitude. The improvement is especially obvious under low OSR conditions. For large power MOSFET drivers, driver circuits with unequal slopes of rising and falling edges are proposed to reduce the imperfection of power stage outputs. To protect this amplifier from short circuits and improper loads, a new over-current protection circuit with high supply-noise rejection and low sensitivity to parameter variation of devices is proposed. This single-chip amplifier is fabricated with a 0.35 um 1P3M 3.3/18-V C/D-MOS process. The total chip area is about 50 mm2. Both peak SNR and dynamic range are 84 dB with an A-weighted function compared to the output noise at full scale input. Both peak SNR and dynamic range are 92 dB compared to the output noise at zero input. The RMS output power of five normal channels on five 8 ohm loads and a subwoofer channel on a 3 ohm load are 13WX5 and 35W, respectively. The total RMS output power is 100W @ a 0.3 % total-harmonic-distortion-plus-noise (THD + N) ratio. The measured minimum THD + N ratio is 0.045 %. The measured maximum power efficiency is 88 %. A 128-pin QFP package with an exposed thermal pad is used. With high power efficiency and the exposed thermal pad, no extra heatsinks are necessary. A low cost 5.1-channel high power amplifier system with a small volume is possible. This is a big design breakthrough in high power 5.1-channel Hi-Fi audio amplifier systems.
In addition to the aforementioned circuit implementations, this dissertation proposes a novel method for increasing linear output power under the same VDD and loads. This method can save power module costs and can be used in future designs. In digital amplifiers, the linear output power range is usually dominated by DSMs. In a conventional single-stage high-order DSM, part of its root locus is outside the unit circle so the stable input range is limited. A new method is proposed for designing a DSM with its root locus inside the unit circle (RLiUC DSM). The RLiUC DSM can maintain a high signal-to-noise plus distortion ratio (SNDR) at the full scale input magnitude. An RLiUC DSM designed using the proposed method with full scale stable input magnitude and a conventional DSM designed with high peak SNDR are combined to extend the linear output power range of digital amplifiers. Methods to implement this combination are also presented. Compared to the digital amplifiers with conventional DSMs, the maximum linear output power is increased by 20 %. Compared to the state-of-the-art design, the output power region which has very low THD + N ratio is extended 160 % by the proposed method.

Abstract (Chinese) I
Abstract (English) III
Acknowledgements V
Contents VI
List of Tables VIII
List of Figures IX

1 Introduction 1
1.1 Overview of Audio Amplifiers …………………………………………… 1
1.2 Class-D Audio Amplifiers………………………………………………… 7
1.3 Motivation ………………………………………………………………… 12
1.4 Organization ……………………………………………………………… 14

2 System Design of a 100W Single-Chip 5.1-Channel Digital-Input Class-D Audio Amplifier 15
2.1 Introduction ………………………………………………………………… 15
2.2 Architecture of a Single-Chip 5.1-Channel Digital-Input Class-D Audio Amplifier …………………………………………………………… 17
2.3 Selection of DSM Structure for a Digital-Input Class-D Audio Amplifier … 20
2.4 Determination of Total Rated Output Power, Thermal Resistance,Power Efficiency and Xinmax …………………………………………… 22
2.5 DSM Design for a Digital-Input Class-D Audio Amplifier ……………… 27
2.6 Effects of Jitter and Nonideal PWM Waveforms ………………………… 34
2.7 Summary ………………………………………………………………… 37

3 Circuit Implementations, Measurement Results, and Demonstration System 38
3.1 Introduction ………………………………………………………………… 38
3.2 Signal Path Circuit Design ………………………………………………… 39
3.3 Protection Circuit Design ………………………………………………… 48
3.3.1 Thermal Protection Circuit ………………………………………… 49
3.3.2 Over-Current Protection Circuit …………………………………… 50
3.4 Measurement Results ……………………………………………………… 57
3.5 A 5.1-Channel Amplifier System ………………………………………… 69
3.6 Summary ………………………………………………………………… 72

4 Single-Stage DSM with Root Loci inside Unit Circle and Its Application to Digital-Input Class-D Audio Amplifiers 73
4.1 Introduction ………………………………………………………………… 73
4.2 Design Method of a Single-Stage High-Order DSM with Root Loci inside Unit Circle ………………………………………………………… 74
4.2.1 Review of Previous Work [43] …………………………………… 74
4.2.2 NTF with Complex-Conjugate Zeros on Unit Circle ……………… 85
4.3 The Proposed Modified Design Method to Improve Noise Attenuation …… 92
4.4 Digital-Input Class-D Audio Amplifier with RLiUC DSM …………… 100
4.5 Summary ………………………………………………………………… 108

5 Conclusion 109

Bibliography 111

Curriculum Vitae 115

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