臺灣博碩士論文加值系統

隨著物聯網設備的快速發展以及普及，物聯網的網絡安全問題已經成為一個重大的挑戰，因為在有限的硬體資源下（例如：頻寬、儲存空間、效能…等），我們將無法藉由純軟體的方式，從這些封包傳遞中找出或分析出隱藏在資料內容中的威脅及病毒，因此需要硬體的支援將大量的封包資料經過快速且精確的比對運算。在這樣的比對加速器，有兩個重要的特徵需要實現彈性（feature-rich）與高效能（energy-efficient）。因此，我們設計了一個比對加速器，它使用了三元內容定址記憶體（TCAM）及非揮發性記憶體（non-volatile memory）來進行關鍵架構的最佳化，因為其具有快速搜尋、平行處理、高效能的特色。
另一方面，面對到網路攻擊與病毒內容的多樣化，需要比對的內容也越來越複雜而其速度也越來越慢，嚴重影響到封包傳遞。我們透過演算法和架構共同設計的方式，來有效的減少比對內容及次數，並且大幅降低所需要的硬體資源，使其可以廣泛的應用在物聯網設備上。

Regular expression matching becomes indispensable elements of Internet of Things (IoT) network security. However, traditional TCAM search engine is unable to handle patterns with wildcards, as it precisely tracks only one active state with single transition. This work proposes a promising Simultaneous Pattern Matching methodology for wildcard patterns by two separated engines to represent Discrete Finite Automata (Discrete-FA). A key preprocessing to encode possible postfix pattern by a unique key ensures that follow-up patterns can accurately traverse all possible matches with limited hardware resources. This approach is practical and scalable for achieving good performance and low space consumption in network security, and it can be applicable to any regular expressions even with multi-wildcard patterns.
Also, Ternary content-addressable memory (TCAM)-based search engines generally need a priority encoder to select the highest priority match entry for resolving the multiple match problem due to the don’t care (X) features of TCAM. However, the use of priority encoder results in increased energy consumption for pattern updates and search operations. Instead of using priority encoders to determine the match, our solution is a three-phase search operation that utilizes the length information of the matched patterns to decide the longest pattern match data. This study proposes a promising memory technology called Priority-Decision in Memory (PDM), which eliminates the need for priority encoders and removes restrictions on ordering, implying that patterns can be stored in an arbitrary order without sorting their lengths. Moreover, we present a Sequential Input-State Search (SIS) scheme to disable the mass of redundant search operations in state segments on the basis of an analysis distribution of hex signatures in a virus database.
On the other hand, non-volatile memory (NVM) has commonly been used to address increasingly large last-level caches (LLCs) requirements by reducing leakage. However, frequent data-writing operations result in increased energy consumption. A promising memory technology, Non-volatile SRAM (nvSRAM), enables normal and standby operation modes which can be used to store various types of data. However, nvSRAM suffers from high dynamic energy usage due to frequent switching between operation modes. In this work, we propose a redundant store elimination (RSE) scheme which, on average, discards 94% of needless bit-write operations. Moreover, we present a retention-aware cache management policy to reduce data updates of cache blocks, based on the correlation between data lifetime and cache types.

摘 要 II
ABSTRACT III
誌 謝 V
TABLE OF CONTENTS VI
LIST OF TABLES X
LIST OF FIGURES XI
I. INTRODUCTION 1
1.1 ARCHITECTURAL PERSPECTIVES FOR NETWORK SECURITY 1
1.2 DISSERTATION WORKS AND CONTRIBUTIONS 5
1.2.1 Simultaneous Discrete Finite Automata for Regular Expression Matching 5
1.2.2 Priority-Decision in Memory for TCAM Search Engine 6
1.2.3 Redundant Store Elimination for Last Level Non-Volatile SRAM Caches 8
1.2.4 Dissertation Works and Contributions 9
II. BACKGROUND 13
2.1 DFA – DETERMINISTIC FINITE AUTOMATA 13
2.2 NFA – NONDETERMINISTIC FINITE AUTOMATA 14
2.3 TCAM SEARCH ENGINE FOR REGULAR EXPRESSION MATCHING 15
2.4 CONVENTIONAL ASYMMETRIC TCAM 17
2.5 CONVENTIONAL SYMMETRIC TCAM 19
2.6 RCSD-4T2R NVTCAM 20
III. SIMULTANEOUS DISCRETE FINITE AUTOMATA FOR REGULAR EXPRESSION MATCHING 23
3.1 RELATED WORK 23
3.1.1 Regular Expression Grouping 23
3.1.2 Transition Compression 24
3.1.3 Hybrid Construction 25
3.1.4 TCAM-Based Search Engines 25
3.2 LIMITATIONS OF HARDWARE SEARCH ENGINES 28
3.2.1 Why Limit the Number of Active States? 28
3.2.2 Restrictions of Single Active State 30
3.3 EFFICIENT SEPARATED TCAM SEARCH ENGINES 33
3.3.1 Hardware Architecture 34
3.3.1.1 Simultaneous Matching Engine 35
3.3.2 Single Wildcard Patterns in Discrete-FA 36
3.3.3 Simultaneous Pattern Matching 39
3.3.4 Resolve Ambiguity in Key Assignment 42
3.4 MULTI-WILDCARD PATTERN 46
3.5 EXPERIMENTAL RESULTS 49
3.5.1 Discrete-FA vs. DFA and NFA 50
3.5.2 Evaluation of Key Matching Engine 52
3.5.3 Performance and Energy Consumption 54
3.5.3.1 Performance Evaluation 55
3.5.3.2 Energy Consumption Improvement 56
3.6 DISCUSSION: USING NON-VOLATILE TCAM IN NETWORK SECURITY 57
3.7 SUMMARY 58
IV. PRIORITY-DECISION IN MEMORY FOR TCAM SEARCH ENGINE 59
4.1 RELATED WORK 59
4.2 WHY NOT USE PRIORITY ENCODER? 60
4.2.1 Limitations of Pattern Update 60
4.2.2 Overhead of Energy Consumption 61
4.3 ENERGY-EFFICIENT NON-VOLATILE TCAM SEARCH ENGINES 63
4.3.1 Three-Phase Search Operation of Priority-Decision in Memory 64
4.3.2 4T2R plus Priority-Decision in Memory 66
4.3.2.1 Search Match Pattern Data 67
4.3.2.2 Find Longest Pattern Length 68
4.3.2.3 Search for the Longest Pattern Match 69
4.4 SYMMETRIC TCAM PLUS PRIORITY-DECISION IN MEMORY 70
4.5 SEQUENTIAL INPUT-STATE SEARCH 72
4.6 EXPERIMENTAL RESULTS 75
4.6.1 Impact of Pattern Update Overhead 75
4.6.2 Improvement of Energy Consumption 77
4.6.3 TCAM vs. 4T2R and 4T2R plus PDM 79
4.7 SYSTEM ARCHITECTURE EVALUATION IN SEARCH ENGINES 80
4.7.1 Energy Evaluation of Search Engines 80
4.7.2 Performance Evaluation in Search Engines 81
4.8 DISCUSSION: APPLICABILITY OF PRIORITY-DECISION IN MEMORY 82
4.9 SUMMARY 83
V. NON-VOLATILE SRAM DESIGN IN LAST LEVEL CACHES 85
5.1 MEMORY CELL PRELIMINARIES 86
5.1.1 SRAM 86
5.1.2 RRAM 87
5.1.3 Non-Volatile SRAM 88
5.2 NVSRAM VS. SRAM AND RRAM 89
5.3 IMPACT OF DATA LIFETIME ON CACHE BLOCK 91
VI. REDUNDANT STORE ELIMINATION FOR LAST LEVEL NON-VOLATILE SRAM CACHES 94
6.1 RELATED WORK 94
6.2 WHY NVSRAM? 95
6.3 ENERGY-EFFICIENT NON-VOLATILE SRAM CACHE ARCHITECTURE 97
6.3.1 Redundant Store Elimination (RSE) 98
6.3.2 Retention-Aware Management Policy 101
6.4 EXPERIMENTAL RESULTS 103
6.4.1 Performance Evaluation 103
6.4.2 Retention Count Evaluation 104
6.4.3 Last-Level Cache Energy Evaluation 106
6.5 SUMMARY 107
VII. CONCLUSION 108
VIII. FUTURE WORK 109
REFERENCES 110

[1] C.R. Meiners, J. Patel, E. Norige, A. X. Liu and E. Torng, “Fast Regular Expression Matching Using Small TCAM,” IEEE Trans. Networking, vol. 22, pp. 94-109, 2014.
[2] M. Alicherry, M. Muthuprasanna and V. Kumar, “High Speed Pattern Matching for Network IDS/IPS,” in Proc. ICNP, 2006, pp. 187-196.
[3] K. Peng, S. Tang, M. Chen and Q. Dong, “Chain-based DFA Deflation for Fast and Scalable Regular Expression Matching Using TCAM,” in Proc. ANCS, 2011, pp. 24-35.
[4] S. Yun, “An Efficient TCAM-Based Implementation of Multipattern Matching Using Covered State Encoding,” IEEE Trans. Comput., vol. 61, pp. 213-221, Feb. 2012.
[5] Y.-D. Kim, H.-S. Ahn, S. Kim and D.-K. Jeong, “A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, pp. 1221-1230, Jun. 2009.
[6] T. Banerjee, S. Sahni and G. Seetharaman, “PC-TRIO: A Power Efficient TCAM Architecture for Packet Classifiers,” IEEE Trans. Comput., vol. 64, pp. 1104-1118, Apr. 2015.
[7] C.-C. Cheng, C.-C. Wang, W.-C. Ku, T.-C. Chen and J.-S. Wang, “A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, pp. 841-854, 2012.
[8] S.K. Maurya and L. T. Clark, “A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, pp. 963-972, Jen. 2011.
[9] Z. Cai, Z. Wang, K. Zheng and J. Cao, “A Distributed TCAM Coprocessor Architecture for Integrated Longest Prefix Matching, Policy Filtering, and Content Filtering,” IEEE Trans. Comput., vol. 62, pp. 417-427, Mar. 2013.
[10] S. Matsunaga, S. Miura, H. Honjou, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno and T. Hanyu, “A 3.14 um2 4T-2MTJ-Cell Fully Parallel TCAM Based on Nonvolatile Logic-in-Memory Architecture,” in Proc. VLSIC, 2012, pp. 44-45.
[11] L.-Y Huang, M.-F. Chang, C.-H. Chuang, C.-C. Kuo, C.-F. Chen, G.-H. Yang, H.-J. Tsai, T.-F. Chen, S.-S. Sheu, K.-L. Su, F. T. Chen, T.-K. Ku, M.-J. Tsai, M.-J. Kao, “ReRAM-based 4T2R Nonvolatile TCAM with 7x NVM-Stress Reduction, and 4x Improvement in Speed-Word Length-Capacity for Normally-Off Instant-On Filter-Based Search Engines Used in Big-Data Processing,” in Proc. VLSIC, 2014.
[12] H.-J Tsai, K.-H. Yang, Y.-C. Peng, C.-C. Lin, Y.-H. Tsao, M.-F. Chang and T.-F. Chen, “Energy-Efficient Non-Volatile TCAM Search Engine Design Using Priority-Decision in Memory Technology for DPI,” in Proc. DAC, 2015.
[13] D.S. Vijayasarathi, M. Nourani, M. J. Akhbarizadeh and P. T. Balsara, “Ripple-Percharge TCAM: A Low-Power Solution for Network Search Engines,” in Proc. ICCD, 2005.
[14] J.-F. Li, “Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, pp. 912-920, Jun. 2010.
[15] K. Hung, L. Ding, G. Xie, D. Zhang, A.X. Liu and K. Salamatian, “Scalable TCAM-based Regular Expression Matching with Compressed Finite Automata,” in Proc. ANCS, 2013.
[16] C.-H. Huang, J.-S. Wang and Y.-C. Huang, “Design of High-Performance CMOS Priority Encoders and Incrementer/Decrementers Using Multilevel Lookahead and Multilevel Folding Techniques,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 63-76, Jan. 2002.
[17] N. Mohan, W. Fung and M. Sachdev, “Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable Memory,” in Proc. SoCC, 2006, pp. 253-256.
[18] Y.-J. Chang, K.-L Tsai and H.-J. Tsai, “Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, pp. 1478-1486, Jun. 2013.
[19] M. Kobayshi, T. Murase and A. Kuriyama, “A Longest Match Search Engine for Multi-Gigabit IP Processing,” in Proc. ICC, 2000.
[20] Y.-F Cheng and Y.-J. Chang, “A Novel High Performance Ternary CAM (TCAM) for LPM,” in Proc. ESA, 2009, pp. 22-27.
[21] R. Govindaraj, I. Sengupta and S. Chattopadhyay, “An Efficient Technique for Longest Prefix Matching in Network Routers,” Progress in VLSI Design and Test. Springer Berlin Heidelberg, 2012, pp. 317-326.
[22] A. T. Do, S. Chen, Z.-H. Kong and K. S. Yeo, “A Low-Power CAM with Efficient Power and Delay Trade-Off,” in Proc. ISCAS, 2011.
[23] S. Baeg, “Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, pp. 1485-1494, Jul. 2008.
[24] S.-H. Yang, Y.-H. Huang and J.-F. Li, “A Low-Power Ternary Content Addressable Memory with Pai-Sigma Matchlines,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, pp. 1909-1913, Oct. 2012.
[25] ClamAV anti-virus system [Online]. Available: http://www.clam-av.net
[26] A. Bremler-Barr, D. Hay and Y. Koral, “CompactDFA: Scalable Pattern Matching Using Longest Prefix Match Solutions,” IEEE Trans. Networking, vol. 22, pp. 415-428, Apr. 2014.
[27] S. Kasnavi, V. C. Gaudet, P. Berube and J. N. Amaral, “A Hardware-Based Longest Prefix Matching Scheme for TCAMs,” in Proc. ISCAS, 2005, pp. 3339-3342.
[28] R. Khan, S.U. Khan, R. Zaheer and S. Khan, “Future Internet: The Internet of Things Architecture, Possible Applications and Key Challenges,” in Proc. ICCSEE, 2012, pp. 257-260
[29] K. Zhao and L. Ge, “A Survey on the Internet of Things Security,” in Proc. CIS, 2013, pp. 663-667.
[30] A. Riahi, Y. Challal, E. Natalizio, Z. Chtourou and A. Bouabdallah, “A systemic approach for IoT security,” in Proc. DCOSS, 2013.
[31] H. Ning and H. Kiu, “Cyber-Physical-Social Based Security Architecture for Future Internet of Things,” in Proc. AIT, 2012.
[32] Z.-K. Ahang, M.C.Y. Cho, C.-W. Wang, C.-W. Hsu, C.-K.Ceen and S. Shieh, “IoT Security: Ongoing Challenges and Research Opportunities,” in Proc. SOCA, 2014F. pp. 230-234.
[33] S.S. Basu, S. Tripathy and A.R. Chowdhury, “Design challenges and security issues in the Internet of Things,” in Proc. TENSYMP, 2015, pp. 90-93.
[34] A. V. Aho and M. J. Corasick, “Efficient String Matching: an Aid to Bibliographic Search,” Communications of the ACM, vol.18, pp.333- 340, 1975.
[35] J. van Lunteren, C. Hagleitner, T. Heil, G. Biran, U. Shvadron and K. Atasu, “Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator” in Proc. MICRO, 2012, pp. 461-472.
[36] K. Atasu, “Resource-Efficient Regular Expression Matching Architecture for Text Analytics,” in Proc. ASAP, 2014, pp. 1-8.
[37] K. Wang, Z. Fu, X. Hu and J. Li, “Practical Regular Expression Matching Free of Scalability and Performance Barriers,” Comput. Commun., vol. 65, pp. 1-119, 2016.
[38] N.L. Or, X. Wang and D. Pao, “Memory-Based Hardware Architectures to Detect ClamAV Virus Signatures with Restricted Regular Expression Features,” IEEE Trans. Computer., vol. 61, pp. 1225-1038, 2016.
[39] P. Piyachon and Y. Luo, “Design of High Performance Pattern Matching Engine Through Compact Deterministic Finite Automata,” in Proc. DAC, 2008. pp. 852-857.
[40] Y. Sun, H. Liu, V.C. Valgenti and M.S. Kim, “Hybrid Regular Expression Matching for Deep Packet Inspection on Multi-Core Architecture,” in Proc. ICCCN, 2010, pp. 1-7.
[41] C. Liu and J. Wu, “Fast Deep Packet Inspection with a Dual Finite Automata,” IEEE Trans. Computer., vol. 62, pp.310-321, 2013.
[42] B.C. Brodie, R.K. Cytron and D.E. Taylor, “A Scalable Architecture for High-Throughput Regular-Expression Pattern Matching,” in Proc. ISCA, 2006, pp. 191-202.
[43] Y.-H.E. Yang, V.K. Prasanna, “Space-Time Tradeoff in Regular Expression Matching with Semi-Deterministic Finite Automata,” in Proc. INFOCOM, 2011, pp. 1853-1861.
[44] M. Becchi and P. Crowley, “A Hybrid Finite Automaton for Practical Deep Packet Inspection,” in Proc. CoNEXT, 2007.
[45] M. Becchi and P. Crowley, “Extending Finite Automata to Efficiently Match Perl-Compatible Regular Expressions,” in Proc. CoNEXT, 2008.
[46] A.N. Arslan, B. Georg and K. Stor, “New Algorithms for Pattern Matching with Wildcards and Length Constraints,” Discrete Mathematics, Algorithms and Applications, vol. 7, pp. 1-13, 2015.
[47] A.N. Arslan, D. He, Y. He and X. Wu, “Pattern Matching with Wildcards and Length Constraints Using Maximum Network Flow,” Journal of Discrete Algorithms, vol. 35, pp. 9-16, 2015.
[48] L. Wang, J. Zhan, C. Luo, Y. Zhu, Q. Yang, Y. He, W. Gao, Z. Jia, Y. Shi, S. Zhang, C. Zheng, G. Lu, K. Zhan, X. Li and B. Qiu, “BigDataBench: a Big Data Benchmark Suite from Internet Services,” in Proc. HPCA, 2014, pp. 488-499.
[49] T. Song, W. Zhang, D. Wang and Y. Xue, “A Memory Efficient Multiple Pattern Matching Architecture for Network Security,” in Proc, INFOCOM, 2008, pp. 673-681.
[50] Y. Sun, V.C. Valgenti and M.S. Kim, “NFA-based Pattern Matching for Deep Packet Inspection,” in Proc. ICCCN, 2011, pp. 1-6.
[51] S. Kumar, S. Dharmapurikar, F. Yu, P. Crowley, and J. Turner, “Algorithms to Accelerate Multiple Regular Expressions Matching for Deep Packet Inspection,” in Proc. SIGCOMM, 2006, pp. 339-350.
[52] M. Bando, N. S. Artan, and H. J. Chao, “Scalable Lookahead Regular Expression Detection System for Deep Packet Inspection,” IEEE/ACM Trans. Netw., vol. 20, pp. 699-714, 2012.
[53] F. Yu, Z. Chen and Y. Diao, “Fast and Memory-Efficient Regular Expression Matching for Deep Packet Inspection,” in Proc. ANCS, 2006.
[54] J. Rohrer, K. Atasu, J. van Lunteren and C. Hagleitner, “Memory-Efficient Distribution of Regular Expressions for Fast Deep Packet Inspection,” in Proc. CODES+ISSS, 2009, pp. 147-154.
[55] A. Majumder, R. Rastogi and S. Vanama, “Scalable Regular Expression Matching on Data Streams,” in Proc. SIGMOD, 2008, pp. 161-172.
[56] D. Ficara, S. Giordano, G. Procissi, F. Vitucci, G. Antichi and A. Di Pietro, “An Improved DFA for Fast Regular Expression Matching,” in Proc. SIGCOMM, 2008, pp. 29-40.
[57] T. Liu, Y. Yang, Y. Liu, Y. Sun and L. Guo, “An Efficient Regular Expressions Compression Algorithm from a New Perspective,” in Proc. INFOCOM, 2011, pp. 2129-2137.
[58] J. van Lunteren and A. Guanella, “Hardware-Accelerated Regular Expression Matching at Multiple Tens of Gb/s,” in Proc. INFOCOM, 2012, pp. 1737-1745.
[59] J. Patel, A.X. Liu and E. Torng, “Bypassing Space Explosion in Regular Expression Matching for Network Intrusion Detection and Prevention Systems,” in Proc. NDSS, 2012, pp. 1-15.
[60] S. Kumar, J. Turner and J. Williams, “Advanced Algorithms for Fast and Scalable Deep Packet Inspection,” in Proc. ANCS, 2006, pp. 81-92.
[61] F. Yu, R. H. Katz, and T. V. Lakshman, “Gigabit Rate Packet Pattern-Matching Using TCAM,” in Proc. ICNP, 2004, pp. 174-183.
[62] C.-H. Lin and S.-C. Chang, “Efficient Pattern Matching Algorithm for Memory Architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, pp. 33-41, 2011.
[63] Y. Weinsberg, S. Tzur-David, D. Dolev, and T. Anker, “High Performance String Matching Algorithm for a Network Intrusion Prevention System (NIPS),” in Proc. HPSR, 2006, pp. 147-154.
[64] S. P. Park, S. Gupta, N. Mojrmder, A. Raghunathan and K. Roy, “Future Cache Design using STT MRAMs for Improved Energy Efficiency: Devices, Circuits and Architecture,” in Proc. DAC, 2012, pp. 492-497.
[65] S.-S. Sheu, M.-F. Chang, K.-F. Lin, C.-W. Wu, Y.-S. Chen, P.-F. Chiu, C.-C. Kuo, Y.-S. Yang, P.-C. Chiang, W.-P. Lin, C.-H. Lin, H.-Y. Lee, P.-Y. Gu, S.-M. Wang, F. T. Chen, K.-L. Su, C.-H. Lien, K.-H. Cheng, H.-T. Wu, T.-K. Ku, M.-J. Kao and M.-J. Tsai, “4 Mb Embedded SLC Resistive-RAM Macro with 7.2 ns Read-Write Random-Access Time and 160 ns MLC-Access Capability,” in Proc. ISSCC, 2011, pp. 200-202.
[66] K. Lee and S. H. Kang, “Development of Embedded STT-MRAM for Mobile System-On-Chips,” IEEE Trans. Magn., vol. 47, 2011.
[67] X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony and Y. Xie, “Hybrid Cache Architecture with Disparate Memory Technologies," in Proc. ISCA, 2009, pp. 34-45.
[68] G. Sun, X. Dong, Y. Xie, J. Li and Y. Chen, “A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs,” in Proc. HPCA, 2009, pp. 239-249.
[69] J. Wang, X. Dong and Y. Xie, “Point and Discard: A Hard-Error-Tolerant Architecture for Non-Volatile Last Level Caches,” in Proc. DAC, 2012.
[70] Y. Zhou, C. Zhang, G. Sun, K. Wang and Y. Zhang, “Asymmetric-access aware Optimization for STT-RAM Caches with Process Variations,” in Proc. GLSVLSI, 2013.
[71] Y. Ma, T. Shibata and T. Endoh, “An MTJ-Based Nonvolatile Associative Memory Architecture With Intelligent Power-Saving Scheme for High-Speed Low-Power Recognition Applications,” in Proc. ISCAS, 2013, pp. 1248-1251.
[72] P.-F. Chiu, M.-F. Chang, C.-W. Wu, C.-H. Chuang, S.-S. Sheu, Y.-S. Chen and M.-J. Tsai, “Low Store Energy, Low VDDmin, 8T2R NonVolatile Latch and SRAM with Vertical-Stacked Resistive Memory (memristor) Devices for Low Power Mobile Applications,” IEEE J. Solid-State Circuits, vol. 47, pp. 1483-1496, Jun. 2012.
[73] M. Rasquinha, D. Choudhary, S. Chatterjee, S. Mukhopadhyay and S. Yalamanchili, “An Energy Efficient Cache Design Using Spin Torque Transfer (STT) RAM,” in Proc. ISLPED, 2010.
[74] P. Zhou, B. Zhao, J. Yang and Y. Zhang, ‘‘A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology,’’ in Proc. ISCA, 2009.
[75] P. Zhou, B. Zhao, J. Yang and Y. Zhang, “Energy Reduction for STT-RAM using Early Write Termination,” in Proc. ICCAD, 2009, pp. 264-268.
[76] R. Ubal, J. Sahuquillo, S. Prtit and P. Lopez, “Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors,” in Proc. SBAC-PAD, 2007.
[77] A. Jaleel, K. B. Theoblad, S. C. Stelly Jr. and J. Emer, “High Performance Cache Replacement using Re-Reference Interval Prediction (RRIP),” in Proc. ISCA, 2010.
[78] J. Wang, X. Dong and Y. Xie, “OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Cache,” in Proc. DATE, 2013.
[79] A. P. Ferreira, M. Zhou, S. Bock, B. Childers, R. Melhem and D. Mosse, “Increasing PCM Main Memory Lifetime,” in Proc. DATE, 2010, pp. 914-919.
[80] S.-Y Park, D. Jung, J.-S. Kim and J. Lee, “CFLRU: A Replacement Algorithm for Flash Memory,” in Proc. CASES, 2006, pp. 234-241.