臺灣博碩士論文加值系統

在現代的超大型積體電路設計中，時鐘樹網路在功率消耗上佔了相當大的一部份。越來越高的操作頻率意味著功率耗費的問題越大。如果不能小心的設計時鐘網路的話，功率消耗的問題會更嚴重。在本篇論文中，我們展示出一個方法能夠在時鐘樹合成時，達到低功率的效果，並且能符合零偏斜的限制。這方法基本上是使用低振幅的連接器來傳送時鐘訊號，且用低振幅、雙邊觸發正反器接收。此外我們可以降低插入的緩衝器數目和減少電線長度以達到低功率的效果。由實驗結果可以得知，我們的方法能有效的降低功率。跟之前使用低振幅傳輸時鐘網路訊號的方法相比，我們能夠減少平均百分之四十五左右的功率消耗。

1 Introduction 1
1.1 Motivation for Designing Low Power Clock Network . . . . . . . . . . 1
1.2 Organization of This Thesis . . . . . . . . . . . . . 2
2 Preliminaries 3
2.1 Previous Works . . . . . . . . . . . . .. . . . . . . 3
2.2 Delay Computation and Skew Constraints . . . . . . . . . . . . . . . 6
2.3 Power Estimation of Clock Network . . . . . . . . . . . . . 8
2.4 Problem Formulation . . . . . . . . . . . . . . . . . 9
3 Low-Swing Buffered Clock Tree 11
3.1 Structure of Low-Swing Clock Tree . . . . . . . . . . 11
3.2 Buffer Insertion . . . . . . . . . . . . . . . . . . 15
4 Low-Swing DME Buffering for Low Power Clock Network Construction
17
4.1 Load Clustering . . . . . . . . . . . . . . . . . . . 17
4.2 DME with Buffer Insertion . . . . . .. . . . . . . 20
4.2.1 Bottom-up phase . . . . . . . . . . . . . . . . 20
4.2.2 Top-down phase . . . . . . . . . . . . . . . . . 22
5 Experimental Results 25
6 Conclusion and Future Work 28
Bibliography 29

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