臺灣博碩士論文加值系統

本論文採用雙路徑頻率補償技術，應用於直流-直流轉換器。此技術使用兩道流向相反之電流，同時對誤差放大器輸出端的補償電容進行充放電。此方法不僅可有效縮小補償電容值，亦可改善轉換器的暫態響應。論文中也提出一緩啟動機制，利用信號控制電流流入電容時間，使參考位準以階梯式方式遞增，以實現抑制浪湧電流與過充電壓。兩種技術皆具有電容放大效應，使得補償電容與緩啟動電容易於製作於晶片內部，以減少外接元件需求。
本轉換器使用TSMC 0.35 μm 2P4M CMOS製程來實現，晶片面積為1.780×1.977 mm2，輸入電壓5 V而輸出電壓3.3 V，外接電感與電容分別為4.7 μH與10 μF，切換頻率則是1 MHz。與其他參考文獻相比，雙路徑電容放大技術能將所需的補償電容值縮小百倍，且當負載電流由50 mA變化至500 mA時，轉換器回復時間小於18 μs。緩啟動電路則有效抑制浪湧電流與過充電壓。

This thesis presents a dual-path frequency compensation technique and implements the technique in a dc-dc converter. This compensation technique uses two currents, whose directions are reversed, to simultaneously charge and discharge the compensation capacitor of the error amplifier. This method not only has capacitor multiplier effect, but also improves the transient response of the dc-dc converter. This thesis also introduces a novel soft-start circuit that uses a signal to control a charging current value into the capacitor of the soft-start circuit. As a result, the voltage reference of the error amplifier increases slowly as a stair-case signal to prevent inrush current and output voltage overshoot during the start-up period. Both of two techniques have capacitor multiplier effect, so the compensation capacitor and soft-start capacitor are easy to be integrated into on-chip. Therefore, it leads to a reduction in external components.
This converter had been fabricated with TSMC 0.35-μm 2P4M CMOS process, and its chip size is 1.173×1.146 mm2. The input voltage is 5 V and the output voltage is 3.3 V. The off-chip inductance and capacitance are 4.7 μH and 10 μF, respectively. The switching frequency is 1 MHz. To compare with other references, the value of compensation capacitor can be reduced by hundred times with dual-path frequency compensation technique and the transient recovery time of the dc-dc converter is less than 18 μs for the load current changing between 50 mA and 500 mA.

摘　要 i
Abstract ii
目　錄 iii
圖目錄 v
表目錄 viii
第一章　緒論 1
1.1 研究背景 1
1.2 研究動機 1
1.3 論文概述 3
第二章　雙路徑頻率補償技術 4
2.1 補償技術之討論 4
2.2 雙路徑電路與緩啟動分析 9
第三章　降壓型轉換器之設計與實現 13
3.1 系統架構 13
3.2 雙路徑電路 14
3.3 緩啟動電路 15
3.4 鋸齒波產生器 17
3.5 電感電流偵測器 19
3.6 斜率補償器 20
3.7 遲滯比較器 23
3.8 具空白時間緩衝器 25
第四章　模擬結果 28
4.1 暫態響應 28
4.2 緩啟動模擬 35
4.3 輸出電壓漣波 39
4.4 電源調節率 39
4.5 負載調節率 40
4.6 效率 41
第五章　晶片量測結果 43
5.1 晶片佈局圖與腳位配置 43
5.2 量測考量 48
5.3 量測結果 49
5.4 文獻比較表與討論 51
第六章　結論與未來展望 52
參考文獻 53

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