臺灣博碩士論文加值系統

本論文探討十二位元連續漸進式(SAR)類比數位轉換器(ADC)之設計與實現。這個ADC架構主要是以連續漸進式類比數位轉換器為基礎，為了降低消耗功率，搭配使用同步時序操作與低電壓運作。另外，本論文提出新的旁通窗式切換應用於心電圖(EKG)。為了滿足十二位元的線性度要求，在數位類比轉換器(DAC)中，使用旁通窗式切換以及電容交換技術，可以得到更好的線性度。
在聯電的180奈米製程下，我們實現兩個連續漸進式類比數位轉換器。第一個類比數位轉換器是一個十二位元同步連續漸進式類比數位轉換器，其晶片面積是0.095平方毫米。在0.7伏特操作電壓以及100 kHz取樣頻率下，功耗是735 nW。量測到的動態效能，有效位元為10.4 bits；訊噪失真比(SNDR)為64 dB；無雜散動態範圍(SFDR)為75dB。在使用電容交換技術之後， SFDR提升到85dB。第二個類比數位轉換器是一個應用於生醫領域十二位元旁通窗式切換連續漸進式類比數位轉換器，其晶片大小為0.274平方毫米。在0.7伏特的操作電壓及100kHz的取樣頻率下，功耗是1.26 W。後模擬結果的動態效能：SNDR 是64 dB，SFDR是80 dB。

This thesis is aimed to present 12-bit Ultra low power successive approximation register (SAR) analog-to-digital converters (ADCs). In order to save the power, the ADC architecture is proposed using the synchronous clocking operation and low voltage supply. Besides, by applying a bypass window for EKG signals. To achieve the 12-bit linearity requirement, the bypass window and capacitor-swapping switching techniques are applied in the DAC.
Two ADCs were implemented in UMC 180 nm CMOS process. The first one is a 12-bit Synchronous-SAR ADC for IoT applications, which occupies an active area of 0.095 〖"mm" 〗^"2" . At 100-MS/s, the ADC consumes a total power of 735nW from a 0.7V supply. The measured ENOB is 10.4 bits. Without the capacitor swapping scheme, the measured SNDR and SFDR are 64 dB and 75 dB, respectively. After using the swapping scheme, the SFDR is improved to 85 dB. The other one is a 12-bit SAR ADC which occupies an active area of 0.274 〖"mm" 〗^"2" . Using a 0.7V supply with the sampling rate of 100 kHz, the total power is 1.26 W. The measured SNDR and SFDR are 64 dB and 80 dB, respectively.

摘要 I
Abstract. II
致 謝…………………………………………………………………III
目 錄…………………………………………………………………IV
圖目錄…………………………………………………………………VII
表目錄………………………………………………………………. X
第一章 緒論 1
1-1 研究動機與目的 1
1-2 章節說明 3
第二章 文獻回顧 4
2-1 各種架構類比數位轉換器之比較 4
2-2 連續漸進式類比數位轉換器 8
第三章 同步時序分析、交換式電容與旁通窗式切換技術 10
3-1 同步時序分析 10
3-1-1 非同步時序分析 11
3-1-2 同步時序分析 12
3-1-3 同步時序之架構 12
3-2 交換式電容技術 14
3-3 旁通窗式切換技術 16
3-3-1 二元窗式切換技術 16
3-3-2 旁通窗式切換技術 18
第四章 一個應用於物聯網的十二位元同步連續漸進式類比數位轉換器之晶片實現 20
4-1 十二位元同步連續漸進式類比數位轉換器之架構 20
4-2 取樣電路 24
4-3 比較器 26
4-4 數位類比轉換器 27
4-4-1 交換式電容技術 28
4-4-2 數位類比轉換器之切換 31
4-4-4 數位類比轉換器電容陣列設計 32
4-5 邏輯控制電路 36
4-6 佈局考量 37
4-7 模擬結果 39
4-8 量測結果 40
4-9-1 實驗設定 40
4-9-2 動態效能 42
4-9-3 靜態效能 44
4-9-4 使用電容交換技術之效能改善 45
4-9-5 結論 47
第五章 一個運用生醫領域的十二位元旁通窗式連續漸進式類比數位轉換器之晶片實現 48
5-1 旁通窗式連續漸進式類比數位轉換器架構 48
5-2 取樣電路 49
5-3 數位類比轉換器之更動 52
5-4 旁通窗式切換分析 55
5-5 連續漸進式控制邏輯電路 58
5-6 模擬結果 60
5-7 佈局考量 62
第六章 結論與未來展望 63
6-1 結論 63
6-2 未來展望 64
參考文獻 65

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