臺灣博碩士論文加值系統

隨著半導體技術的進步，元件的尺寸不斷的縮小，電子訊號在金屬導線間傳遞所造成的延遲，變成半導體元件速度受限的主要原因。為了降低訊號傳遞的時間延遲，使用低介電常數材料作為導線間的絕緣層，便可降低導線間的電容值，使元件在速度方面的性能提高， 並且可以降低功率的消耗及雜訊干擾。但是多孔性低介電常數材料的機械強度一般來說都較緻密的材料差，因此在應力作用是很重要的。
本文研究的是討論低介電材料蝕刻後之特性並且導入銅製程。使用CF4/Ar氣體蝕刻後的特性依實驗結果可分成3部分討論，第一階段是討論氣體對蝕刻後之電性化學物理性質之影響，第二階段是找出蝕刻率與最佳之蝕刻輪廓，第三階段是目的在於研究銅、擴散阻障層TaN與低介電常數材料之製程整合時產生之熱應力之討論。實驗的結果得知在經過CF4/Ar，不同比例蝕刻出來後的結果發現薄膜的抗水性上升，K值有降低的情形。蝕刻後化學成份均類似，因此表面粗糙度為影響其漏電流的要素之一。高密度電漿蝕刻的系統參數當中，我們由實驗過程可以發現：對low-k的乾蝕刻而言，CF4以及Ar的混合氣體可以達到不錯的蝕刻效果。其中當Ar比例為百分之二十的時候為最佳化的條件。由實驗與ANSYS之分析模擬結果，線寬越小內應力越大。

As ULSI are scaled down to deep submicron regime, interconnect delay becomes a increasingly dominant at intrinsic gate delay. Many new low dielectric constant materials have been developed to reduce the RC delay. However, the mechanical strength of porous low k materials is weaker than traditional low-k materials. The discussion of internal stress in the low-k material becomes a very important issue.
This paper investigated the effect of etching of ultra low-k material and the integration process of copper interconnects. Experimental results showed that etching (CF4/Ar) characteristics could be discussed by three parts. In part 1, we discussed about the electrical, chemical and physical characteristic. In part 2, the experiments have been carried out to find the optimal performance etching rate parameters.In part 3, we discussed the integration of copper, diffusion barrier TaN and low-k material. We fabricated a diffusion barrier layer, TaN, low-k dielectric and developed the processes integration for Cu metallization. The investigation of the stress mechanism for damascene structure was analyzed by software.
We know that after CF4/Ar treatment, the different ratios would cause the rise of waterproof and the K value reduced. The chemical compositions were similar as as-deposition. Therefore, the level of surface roughness was one of the factors that influenced the leakage current. Among parameters of HDP system, it is observed that mixed gases of CF4 and Ar are suitable for the low-k plasma etching. And based on our experiment, the optimal condition is obtained with the Ar ratio reaches 20%. According to the experimental and ANSYS results, the smaller linewidth had larger internal stress.

目錄
第一章 前言………………………………………………….………. 1
第二章 文獻回顧…………………………………………….………. 3
2-1 時間延遲效應…………………………………………….……… 3
2-2 金屬導線的選擇……………………………………….………… 6
2-2-1 銅與其他金屬導線之比較…………………….….……….. 6
2-2-2 銅導線沈積技術………………………………..………….. 7
2-2-3 銅金屬化製程……………………………….…………….. 11
2-3 低介電質材料之選擇…………………………………………… 13
2-3-1 低介電質材料條件……………………………..………… 13
2-3-2 低介電材料沈積方式………………………..…………… 14
2-3-3 介電質高低的主要因素…………….……………….…… 15
2-4 阻障層的選擇…………………………………………………… 17
2-4-1 阻障層的種類……..………..…………………………… 17
2-4-2 阻障層的熱穩定性……………………………………… 17
2-4-3 擴散阻障層的沈積方式………………………………… 18
2-5 蝕刻機制……………………………………………………….. 21
2-5-1 蝕刻製程種類………………………………………….... 21
2-5-2傳統SiO2的蝕刻與電漿蝕刻……………….……………. 21
2-6 應力分析………………………………………………………… 23
2-6-1 薄膜殘留應力………………………………………...…... 23
2-6-2 內質應力成因…………………………………………..… 24第三章 實驗方法………..…………………………………………... 30
3 實驗流程…...……………………………………………………… 30
3-1低介電質薄膜製作流程………………………………………31
3-1-1 清洗晶片之程序…………………………………………... 31
3-1-2 實驗配方之藥劑…………………………………………... 32
3-1-3低介電薄膜之製作方法……………………………………. 33
3-2 蝕刻……………………………………………………………... 35
3-2-1電性分析……….……………………...…………………… 35
3-2-2化性分析…………………………...………………………. 36
3-2-3物性分析………………….…………………………………37
3-3 蝕刻輪廓製程流程………………………………………………39
3-4 應力分析流程………..…………………………………………..40
3-4-1模擬試片之樣式與材料參數………………..…………….41
3-4-2 求邊界應力穩定…………………………………..…...…42
3-4-3 模擬不同結構對熱應力之影響………………………….43
3-4-4 模擬結果與實驗搭配…………………………………….43
3-4-5 Low-k與SiLK之比較……………………………………43
第四章 結果討論……..………………..………...…….……………. 46
4-1 薄膜之蝕刻後特性比較……………………….……………46
4-1-1 純CF4蝕刻後之薄膜特性………………….…….……….46
4-1-2 CF4/Ar搭配後蝕刻結果…………………………….…….48
4-1-3 CF4與CHF3蝕刻後之比較……………………………….49
4-2蝕刻輪廓…………………………………………………………. 51
4-2-1 CF4=50蝕刻後輪廓…………………………………..…... 51
4-2-2 CF4/O2=40/10蝕刻後輪廓……………………………….. 51
4-2-3 CF4/O2=25/25蝕刻後輪廓……………………………….. 51
4-2-4 CF4/O2=10/40蝕刻後輪廓……………………………….. 51
4-2-5 CHF3=50 蝕刻後輪廓…………………………………….52
4-2-5 結論……………………………………………………… 52
4-3熱應力分析………………………………………………………53
4-3-1 薄膜熱應力分佈分析……………………………………53
4-3-2 有限元素軟體……………………………………………53
4-3-3材料參數…………………………………………………..54
4-3-4邊界應力分佈……………………………………………..54
4-3-5模擬之結果與實驗的搭配………………………………..55
4-3-6 Low-k與Silk比較……………………………………….57
第五章 結論……………………………………………………………61
參考文獻………………………………………………………………..86

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