臺灣博碩士論文加值系統

本研究藉由VBIC等效電路模型來建立In0.4Ga0.6As0.8Sb0.2異質接面雙極性電晶體之元件模型。參數建立過程中藉由儀器HP 4155B來量測元件之直流特性，並萃取出等效電路模型參數。在使用VBIC等效電路模型依序萃取直流參數時，先建立不含非理想效應之基本直流特性模型，再進一步考慮非理想效應之影響後再建立相關溫度參數。
研究中將不採用反向操作量測的方式來獲得所需之參數，而是藉由Advanced Design System (ADS) 模擬軟體有效地萃取出所需之相關參數，以避免可能因反向操作量測對元件產生不良之影響。另外，於元件模型建立過程中得知，順向Gummel polt模擬與量測結果之擬合程度會影響到電流輸出特性之模擬結果與量測數據是否擬合，故順向Gummel plot之參數萃取為建立元件模型過程中最基本且重要的考量因素。由電流輸出特性集極電流對集射偏壓之關係，從不同偏壓範圍可明確地判斷出元件直流特性是否受爾力效應、自發熱效應以及崩潰效應所影響。本研究藉由加入各個不同的非理想效應來修正萃取之結果，以建構出完整之元件模型。

This thesis summarizes extraction of DC parameters and thermal parameters in VBIC equivalent circuit model for In0.4Ga0.6As0.8Sb0.2 hetero-junction bipolar transistors. Both critical and negligible parameters are pointed out in order to obtain an accurate model. To reduce the time spent in measurement and extract parameters efficiently, the extraction focuses on forward mode operation and neglects reverse mode operation. Parameters for reverse operation are used to optimize the collector current versus collector-emitter voltage (IC-VCE) output characteristic. In the forward Gummel plot, ideal current region is essential for initial parameters extraction, and high current region is important for obtaining a satisfying result in the IC-VCE output characteristic. Early effect, self-heating effect, and avalanche breakdown effect are considered in the IC-VCE output characteristic. This extraction procedure is efficient and the VBIC model parameters are validated by ADS simulation.

摘要.....................................i
ABSTRACT…………………………………………ii
誌 謝……………………………………………iii
目 錄……………………………………………iv
表目錄 …………………………………………vi
圖目錄…………………………………………xii
第一章 簡介…………………………………1
第二章 HBT基本工作原理…….……………4
2.1 HBT 操作原理…………4
2.2 HBT 之直流特性………5
第三章 異質接面電晶體VBIC 訊號模型之介紹與萃取方法…………8
3.1 VBIC 模型之建構 ......9
3.2 獨立基極電流參數………13
3.3 Gummel plot 之電流參數萃取…15
3.4 爾力效應(基極寬度調變，Base Width Modulation)……19
3.5 寄生電阻參數…………………20
3.5.1 射極電阻 (Emitter resistor, RE).………20
3.5.2 集極電阻 (Collector resistor, RC) ...…21
3.5.3 基極電阻 (Base resistor, RB)…...23
3.6 類飽和效應萃取 （Quasi-saturation）………24
3.7 雪崩崩潰 (Avalanche Breakdown)………………………25
3.8 相關溫度參數之建立……………27
第四章 VBIC大訊號模型之建立…………………...34
4.1 元件架構…………………………………………………34
4.2 室溫下VBIC大訊號模型之建立…35
4.2.1 直流參數之萃取……35
4.2.2 爾力效應參數萃取……37
4.3 熱阻參數萃取……………………39
4.3.1 溫度對VBE偏壓的影響.........39
4.3.2 溫度對直流增益β的影響…………………………43
4.3.3 萃取元件熱阻…………45
4.4 VBIC model 量測與模擬結果差異之探討…………………49
4.5 VBIC大訊號模型崩潰參數調整 ...........54
4.6 VBIC熱參數模型之建立 …………55
第五章 結論…………………………………………59
參考文獻…………………………………………………60
附錄一 VBIC model 參數表示法及其物理意義………63
自傳………………………………………………………67

[1]W. Shockley and H. Kroemer, “Theory of Wide-gap Emitter for Transistors”, IRE, vol. 45, pp. 1535, 1998.

[2]Shu-Han Chen, Student Member, Sheng-Yu Wang, Rei-Jay Hsieh, and Jen-Inn Chyi, Senior Member, “InGaAsSb/InP Double Heterojunction Bipolar Transistors Grown by Solid-Source Molecular Beam Epitaxy”, IEEE Electron Device Letters, vol. 28, No. 8, August, 2007.

[3]C. C. McAndrew, et al, “VBIC95, The Vertical Bipolar Inter-Company Model”, IEEE J. Solid-State Circuits, vol. 31, pp. 1476-1483, October, 1998.

[4]H. K. Gummel, and H. C. Poon, “An integrated charge control model of bipolar transistors”, Bell Syst. Tech. J., 49, pp. 827-852, 1970.

[5]Shu-Han Chen, Sheng-Yu Wang, Rei-Jay Hsieh and Jen-Inn Chyi, “ Low turn-on and high-speed InP/InGaAsSb/InGaAs HBTs with an InGaAsSb Base”, Department of Electrical Engineering, National Central University Chung-Li, Taiwan, R.O.C. , p. 17.

[6]黃國威、鄧裕民、管瑞豐、陳良波， “BJT之VBIC模型化技術”， 國家奈米元件實驗室，奈米通訊，第六卷第四期42。

[7]Agilent Technologies, “IC-CAP Modeling Reference”, pp. 6-52, 2000.

[8]張芷娟，磷化銦異質接面雙極性電晶體之等效電路模型，國立雲林科技大學，碩士論文， 2005。

[9]William Liu, “HANDBOOK OF III-V HETEROJUNCTION BIPOLAR TRANSISTOR”, John Willy & Sons, pp. 1088-1090, 1998.



[10]C. C. McAndrew and L. W. Nagel, “SPICE Early Modeling”, Bipolar/BiCOMOS Circuits & Tech. Meeting, pp. 144-147, 1994.

[11]徐慧芬，“VBIC模型應用於不同尺寸異質接面雙載子電晶體之研究”，國立雲林科技大學，碩士論文，2005。

[12]陳駿逸， “VBIC等效模型對異質接面雙載子電晶體之研究”，國立雲林科技大學，碩士論文，pp. 40-44，2003。

[13]李文雄， “磷化銦異質接面雙極性電晶體熱阻與崩潰效應之特性分析”，國立雲林科技大學，碩士論文，2007。

[14]G. M. Kull, L. W. Nagel, S.-W. Lee, P. Lloyd, E. J. Prendergast, and H. K. Dirks, “A Unified Circuit Model for Bipolar Transistors Including Quasi-Saturation Effect”, IEEE Trans. Electron Devices, vol. 32, pp. 1103-1113, 1985.

[15]William Liu, “Handbook of III-V Heterojunction Bipolar Transistors”, John Wiley & Sons, pp. 238-241, 1998.

[16]F. Lin, B. Chen, T. Zhou, B. L. Ooi, P. S. Kooi, “Characterization and Modeling of Avalanche Multiplication in HBTs”, Microelectronics Journal, vol. 33, pp. 39-43, 2002.

[17]HBT Model Manual, Global Communication Semiconductor, Inc., 1999.

[18]D. A. Neamen, “Semiconductor Physics and Device”, 3th ed. McGraw. Hill, pp. 398, 2003.

[19]Kenji Kurishima, Hiroki Nakajima, Takashi Kobayashi, Yutak Matsuoka andTadao Ishibashi, “Fabrication and Characterization of High-Performance InP/InGaAs Double-Heterojunction Bipolar Transistors”, IEEE Trans. Electron Devices, vol. 41, No. 8, pp. 1319-1326, August, 1994.

[20]劉佳慧，“異質接面雙載子電晶體熱效應之研究”，國立雲林科技大學，碩士論文，2002。

[21]D. E. Dawson, A. K. Gupta, and M. L. Salib, “CW Measurement of HBT Thermal Resistance”, IEEE Trans. Electron Devices, vol. 39, pp. 2235-2239, October, 1992.

[22]J. R. Waldrop, K. C. Wang, and P. M. Asbeck, “Determination of Junction Temperature InAlGaAs/GaAs Heterojunction Bipolar Transistors by Electrical Measurement”, IEEE Trans. Electron Devices, vol. 39, pp. 1248-1250, May, 1992.

[23]N. Bovolon, P. Baureis, J.-E. Müller, P. Zwicknagl, R. Schultheis, and E. Zanoni, “A Simple Method for The Thermal Resistance Measurement of AlGaAs/GaAs Heterojunction Bipolar Transistors”, IEEE Trans. Electron Devices, vol. 48, pp. 1846-1848, August, 1998.

[24]Hong Wang, Hong Yang, K. Radhakrishnan and Chee Leong Tan, “On the Thermal Resistance of Metamorphic and Lattice-Matched InP HBTs: A Comparative Study”, Indium Phosphide and Related Materials Conference, IPRM. 14th, pp. 177-180, May, 2002.

[25]S. P. Marsh, “Direct Extraction Technique to Derive the Junction Temperature of HBT’s Under High Self-Heating Bias Conditions”, IEEE Trans. Electron Device, vol. 47, No. 2, pp. 288-291, 2000.

[26]S. P. Marsh, “Thermal Impedance Variation of HBT’s at High Junction Temperature Operating Conditions”, IEEE Trans. Electron Device, pp. 634-637, 1999.