臺灣博碩士論文加值系統

本文針對有線通訊系統的類比前端收發電路提出新的技巧應用於增加CMOS積體電路傳送端驅動器及接收端限幅放大器的效能。這些電路技巧展示在一個20-Gb/s傳送端驅動器使用了標準的RF CMOS 0.13-μm和一個10-Gb/s接收端限幅放大器中使用了標準的RF CMOS 0.18-μm RF CMOS製程. 上述二個電路設計的效能皆可與使用昂貴先進III-V製程相提並論而且由於低晶片功耗與小晶片面積等優點更適合與CMOS SERDES/CDR/CODEC電路做系統式的整合。
所設計的20-Gb/s傳送端雷射光電調變器驅動器由一個並-串式電感peaking (shunt-series inductor peaking) 前級驅動器及一個電感式當地迴授網路 (inductive local feedback network) 輸出級驅動器組成。串-並電感peaking電路技術可以共振掉電晶體本身的寄生電容而電感式自迴授網路可有效的增加電晶體的高頻增益及輸出震幅。所設計的雷射調變驅動器特性為：操作電壓1.2/4.0V雙電壓、消耗功率900 mW、大訊號增益26 dB、波形上升時間< 22ps、單端輸出震幅3.5Vpp、晶片面積0.9 × 0.8 mm2。
所設計的10-Gb/s接收端限幅放大器由一個等化器輸入級、一個電流式邏輯輸出級及一個增益級組成而其中使用了數個電路技巧包括主動電感式peaking (active-load inductive peaking)、Cherry-Hooper式電流主動回饋 (active feedback with current buffer in Cherry-Hooper topology) 和增益控制 (gain control)。所設計的限幅放大器特性為：操作電壓1.8 V、消耗功率85-mW、小訊號增益40-dB、動態範圍40-dB、差動輸出震幅600-mVpp、電路頻寬8 Ghz、晶片面積0.7 × 0.4 mm2。

This study proposes several circuit design techniques to achieve high performance CMOS transceiver chipset for wire-line communication. The circuit concepts are demonstrated by a 20-Gb/s CMOS 0.13-μm laser/modulator driver design and a 10-Gb/s CMOS 0.18-μm limiting amplifier design. The performance evaluation are as good as the advanced expensive III-V compound technology and the fabricated CMOS circuits are suitable for further integration with SERDES, CDR, and CODEC ICs for wire-line communication due to the small die size and low power consumption. The proposed 20-Gb/s laser/modulator driver is fabricated in 0.13-µm mixed-signal 1.2/2.5V 1P8M CMOS process. This work consists of a shunt-series inductor peaking pre-driver stage and a pre-emphasis output driver stage with source de-generation configuration including inductive local feedback network to enhance the operation bandwidth. The data rate is measured up to 20-Gb/s with 3.5VPP S.E. output amplitude in driving 50-Ω output load when the input amplitude is less than 0.15VPP and the rise/fall time of output waveform is less than 22-ps. The total power consumption is 900-mW with 1.2/4.0V dual supply and the chip die size is 900×800-µm2. The proposed 10-Gb/s current mode logic (CML) limiting amplifier is fabricated in 0.18-µm 1P6M CMOS process. This work consists of input equalizer, CML output buffer and gain stages with active-load inductive peaking, duty cycle correction (DCC) and gain control features. The circuit techniques include active load inductive peaking, source de-generation peaking and active feedback with current buffer in Cherry-Hooper topology to enhance operation bandwidth. The proposed design provides 600-mVpp differential voltage swing in driving 50-Ω output loads, 40-dB input dynamic range, 40-dB voltage gain and 8-mVpp input sensitivity. The total power consumption is 85-mW with 1.8V supply and the chip die size is 700×400-µm2.

Abstract 2
Acknowledgements 4
Contents 5
List of Figures 7
List of Tables 11
Chapter I: Introduction 12
1.1 Background and Motivation 12
1.2 Wireline Communication Systems 15
1.3 Preview of Proposed CMOS Front-end Transceiver IC 18
1.4 Organization of Dissertation 20
Chapter II: Gain-Bandwidth Enhancement Techniques 21
2.1 Fundamental Theory Review 21
2.2 Active Inductor Load Peaking 24
2.3 Shunt-Series Inductor Peaking 26
2.4 Negative Feedback Network 29
2.5 Intrinsic Cgd Feedback Network 35
Chapter III: Design of a 10-Gb/s Limiting Amplifier 42
3.1 Introduction 42
3.2 Circuit Architecture 43
3.3 CML Equalizer 44
3.4 CML Gain Stage 47
3.5 CML Output Buffer 50
3.6 Measurement Results 54
3.7 Summary 58
Chapter IV: Design of 10~20-Gb/s Laser/Modulator Drivers 60
4.1 Introduction 60
4.2 Circuit Architecture of Laser/Modulator Driver Design I 62
4.3 Pre-Driver Stage 64
4.4 Post-Driver Stage 67
4.5 Measurement Results 74
4.6 Summary 79
4.7 Circuit Architecture of Laser/Modulator Driver Design II 80
4.8 Output Driver Stage 82
4.9 Measurement Results 86
4.10 Summary 87
Chapter V: Future Work and Conclusion 88
5.1 Future Work 88
5.2 Conclusion 88
References 90
Vitae 94
Publication List 96

[1] Tetsuya Miki, “Optical Network Research and Next Generation High speed Networks,” May 2007.
[2] B. Datta, “High Speed I/O testing: trend and challenges,” Sep. 2005.
[3] S. Palermo, “Lecture 26: High-Speed I/O Overview,” Sep. 2010.
[4] R. Bond, “ITU PON – Past, Present, and Future,” July 2008.
[5] J. Ichikawa, “Technical Trend of LiNbO3 Optical Modulator,” Mar. 2008.
[6] M. Duelk and P. Winzer, “DQPSK Format for Serial PHY,” Nov. 2006.
[7] Altera White Paper, “The Evolution of High-Speed Transceiver Technology,” Nov. 2002.
[8] S. Galal and B. Razavi, “10 Gb/s limiting amplifier and laser/modulator driver in 0.18-μ m CMOS technology,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2138–2146, Dec. 2003.
[9] R. Tao and M. Berroth, “10 Gb/s Limiting Amplifier for Optical links,” IEEE International Solid-State Circuits Conference (ISSCC), Sep. 2003.
[10] P. Muller and Y. Leblebici, “Limiting Amplifier for Next-Generation Multi-Channel Optical I/O interface in SoC,” IEEE SoC Conference, pp. 193-196, Sep. 2005.
[11] W. Z. Chen, Y. L. Cheng, and D. S. Lin, “A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1388–1396, Jun. 2005.
[12] W. Z. Chen and C. H. Lu, “A 90-dBΩ 10-Gb/s Optical Receiver Analog Front-End in a 0.18-μm CMOS Technology,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 3, pp. 358–365, Mar. 2007.
[13] C. S. Chang, D. S. Lee and Y. S. Jou, “Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering,” Computer Communications, vol. 25, pp. 611-622, 2002.

[14] C. S. Chang, D. S. Lee and C. M. Lien, “Load balanced Birkhoff-von Neumann switch, part II: Multi-stage buffering,” Computer Communications,” vol. 25, pp. 623-634, 2002.
[15] C. S. Chang, D. S. Lee, and C. Y. Yue, “Providing guaranteed rate services in the load balanced Birkhoff-von Neumann switches,” Proceedings of IEEE INFOCOM, 2003.
[16] C. S. Chang, D. S. Lee and Y. J. Shih, “Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets,” Proceedings of IEEE INFOCOM, 2004.
[17] E. M. Cherry and D. E. Hooper, “The design of wide-band transistor feedback amplifier,” Inst. Elec. Eng. Proc., vol. 110, no. 2, pp. 375–389, Feb. 1963.
[18] H. Tamura, M. Kibune, H. Yamaguchi, K.Kanda, K. Gotoh and J. Ogawa, “Circuits for CMOS High-Speed I/O in Sub-100nm Technologies,” IEICE Trans. Electron., vol. E89–C, no.3, pp.300-313, Mar. 2006.
[19] Y. Tomita, M. Kibune, J. Ogawa, and W. W. Walker, “A 10Gb/s Receiver with Equalizer and On-chip ISI Monitor in 0.11µm CMOS,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp.202-205, June. 2004.
[20] E. A. Crainl, and M. H. Perrott, “A 3.125Gb/s Limit Amplifier in CMOS with 42dB Gain and 1us Offset Compensation,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 443–451, Feb. 2006.
[21] M.I. Elmasry and P.M. Thompson , “Analysis of load structures for current-mode logic,” IEEE J. Solid-State Circuits, vol. 10, Issue 1, pp.72-75, Feb. 1975.
[22] R. L. Treadway, “DC analysis of current mode logic,” IEEE Circuits and Devices Magazine, vol. 5, Issue 2, pp.21-35, Mar. 1989.
[23] Payam and Heydari, “Design Issues in Low-Voltage High-Speed Current-Mode Logic Buffers,” ACM Great Lakes Symposium on VLSI, pp. 28-29, Apr. 2003.
[24] N. Krishnapura, M. B. Pour, Q. Chaudhry, J. Khoury and A. Aggarwal, “A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission,” IEEE International Solid-State Circuits Conference, pp.60-62, Feb. 2005.
[25] L. Zhao and H. Shankar, “40G QPSK and DQPSK Modulation,” Inphi Corporation, Sunnyvale, California.
[26] H. Ransijin, G. Salvador and D.D. Daaughetry, “A 10-Gb/s Laser /Modulator Driver IC With a Dual-Mode Actively Matched Output Buffer,” IEEE J. Solid-State Circuits, vol. 36, no. 9, pp. 1314–1320, Sep. 2001.
[27] A. Maxim, “A 12.5Gb/s Electro-Absorption-Modulator Driver Using an Adaptive Compensated Push-Pull Emitter Follower and a Cascode Output Switch With Dynamic Headroom Allocation ,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2127–2143, Sep. 2006.
[28] Y. Baeyens, N. Weimann, and P. Roux, “High Gain-Bandwidth Differential Distributed InP D-HBT Driver Amplifier With Large Output Swing at 40Gb/s,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1697–1705, Oct. 2004.
[29] S. Galal and B. Razavi, “40-Gb/s Amplifier and ESD Protection Circuit in 0.18-µm CMOS Technology ,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2389–2396, Dec. 2004.
[30] S. Shekhar, J.S. Walling, and D.J. Allstot, “Bandwidth Extension Techniques for CMOS Amplifiers ,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2424–2439, Nov. 2006.

[31] J.C. Chien, and L.H. Lu, “A 20-Gb/s 1:2 Demultiplexer With Capacitive-Splitting Current-Mode-Logic Latched,” IEEE J. Solid-State Circuits, vol. 55, no. 8, pp. 1624–1631, Aug. 2007.
[32] R. C. Liu, C. S. Lin and K.L. Deng, “Design and Analysis of DC-to-14-Ghz and 22-GHz CMOS Cascode Distributed Amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1370–1374, Aug. 2004.
[33] D.U. Li and C.M. Tsai, “10-Gb/s Modulator Drivers With Local Feedback Networks,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1025–1030, May. 2006.
[34] S. Mandegaran and A. Hajimiri, “A Breakdown Voltage Multiplier for High Voltage Swing Drivers,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 302–312, Feb. 2007.
[35] C.H. Wu, C.H. Lee and W. S. Chen, “CMOS Wideband Amplifiers Using Multiple Inductive-Series Peaking Technique,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 548–552, Feb. 2005.
[36] E.Ayranci, K. Chritensen, P. Andreani, “45% Power Saving in 0.25-μm BiCMOS 10Gb/s 50Ω-Terminnated Packaged Active-Load Laser Driver,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2007.
[37] S. Morley, “A 3V 10.7Gb/s Differential Laser Diode Driver with Active Back-Termination Output Stage,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2005.
[38] C.M. Tsai and M.C. Chiu, “A 10Gb/s Laser-Diode Driver with Active Back-Termination in 0.18-μm CMOS,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2008.
[39] H. Tran, F. Pera, D.S. McPherson, D. Viorel and S.P. Voinigescu, “6-kΩ 43-Gbs Differential Transimpedance-Limiting Amplifier with Auto-zero Feedback and High Dynamic Range,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1680–1689, Feb. 2004.
[40] H. Shigematsu, M. Sato, T. Hirose, F. Brewer and M. Rodwell, “40 Gbs CMOS distributed amplifier for fiber-optic communication systems,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2004.
[41] C.F. Liao and Shen-Iuan Liu, “40G Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 642–655, March 2008.
[42] E. Kerherve and C.P. Moreira, P. Jarry and L. Courcelle, “40G Wide-band MMIC pHEMT Modulator Driver Amplifiers Designed with the Real Frequency Technique,” IEEE Trans. on Microwave Theory and Techniques, vol. 53, no. 6, pp. 2145–2152, June 2005.

[43] A. Yazdi, D. Lin and P. Heydari , “A 1.8 V Three-stage 25GHz 3dB-BW Differential Non-Uniform Downsized Distributed Amplifier,” IEEE International Solid-State Circuit Conference (ISSCC), Feb. 2005.
[44] Y. H. Hsu, M., “A 1V 4.2mW Fully Integrated 2.5Gbs CMOS Limiting Amplifier using Folded Active Inductors,” in proceedings IEEE International Symposium on Circuits and Systems (ISCAS), pp.1044-1047, 2004.
[45] E. Sackinger and W. Fischer, “A 3-GHz 32-dB CMOS Limiting Amplifier for SONET OC-48 Receivers,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1884–1888, Dec. 2000.
[46] J.W. Fattaruso and B. Sheahan, “A 3-V 4.25-Gbs Laser Driver with 0.4-V Output Voltage Compliance,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1930–1937, Aug. 2006.
[47] H.y. Huang, J.C. Chien and L.H. Lu, “A 10-G Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1111–1120, May 2007.
[48] J. Kim and J.F. Buckwalter, “A 40G Optical Transceiver Front-end in 45nm SOI CMOS,” in proceedings IEEE Custom Integrated Circuits Conference (CICC), Sep. 2010.
[49] E. Kerherve and C.P. Moreira, P. Jarry and L. Courcelle, “A Matrix Amplifier in 0.18-um SOI CMOS,” IEEE Trans. on Circuit and System--I: Regular Paper, vol. 53, no. 3, pp. 561–568, March 2006.
[50] B. Analui and A. Hajimiri, “Bandwidth Enhancement for Transimpedance Amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1263–1270, Aug. 2004.
[51] S.S. Mohsn, M.M. Herdhrnson, S.P. Boyd and T.H. Lee, “Bandwidth extension in CMOS with optimized on-chip inductors,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 346–355, March 2000.
[52] H.H. Hsieh, J.H. Wang and L.H. Lu, “Gain-Enhancement Techniques for CMOS Folded LNA,” IEEE Trans. on Microwave Theory and Techniques, vol. 56, no. 8, pp. 1807–1816, Aug. 2008.
[53] S.S. Mohsn, M.M. Herdhrnson, S.P. Boyd and T.H. Lee, “SiGe Driver Circuit with High Output Amplitude Operating up to 23Gb/s,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 886–891, June 1999.