臺灣博碩士論文加值系統

近年來電子產品已朝向高速度與高密度化發展，更進一步，電路設計皆以低操作電壓和低功率來進行設計，這些將造成電源輸送系統（Power Delivery System, PDS）容易受輸入訊號耦合到電源平面的影響，使電源產生不穩定的雜訊。其中同步切換雜訊是影響電源輸送系統的主因，此雜訊將造成電源完整性（Power Integrity, PI）的問題，最後，當雜訊超過容忍範圍，將會使輸出訊號產生錯誤動作，也即造成訊號完整性（Signal Integrity, SI ）的問題。一般是使用去耦合電容抑制同步切換雜訊，但是此方式無法有效降低雜訊。因此，我們提出一套有效法則來建構一個具有抑制雜訊的增強模組以提高電源輸送系統的完整性。當傳統IBIS模型以我們所提出方法論加上去耦合電容和增強模組時，在抑制同步切換雜訊的能力上分別比使用去耦合電容方式提高58.3%、比HSPICE模型提高59.8%，也比傳統IBIS模型提高73.2%。因此，我們的方法可提供給IC或系統設計者以增進其本身抗同步切換雜訊之能力。

Modern electronics products must have improved characteristics, including high-speed, high-density, lower-voltage, low-power consumption operations. With such designs, the power-delivery system (PDS) is affected by the input noise and then becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity (PI). Finally, when this noise excesses its tolerating range, it causes of the wrong operations of output signal, which is called the signal integrity (SI) issue. Generally, most traditional mechanisms have used decoupling capacitors to reduce SSN. Such designs cannot effectively reduce SSN. Therefore, we propose a novel noise-aware design, namely the enhanced IBIS model, to effectively reduce SSN and promote the stability of PI in this thesis. In this thesis, we propose a novel design based on an enhanced I/O buffer information specification mode to be designed in integrated circuit chips that effectively reduces the noise by over 58.3, 59.8, and 73.2% compared with the traditional de-coupling capacitor, HSpice, and IBIS model methods, respectively. Hence, our proposed module can be designed in IC chip and effectively to prevent SSN.

目　錄

摘　要 i
ABSTRACT ii
誌　謝 iii
目　錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1. 研究動機與目的 5
1.2. 論文架構 6
第二章 基本架構與原理 7
2.1. IBIS模型的架構 7
2.1.1. I-V曲線 8
2.1.2. V-T曲線 10
2.1.3. 測試電路參數 13
2.2. 同步切換雜訊的原理 14
2.3. 去耦合電容 16
2.3.1. 特性 16
2.3.2. 用途與使用方法 17
2.4. IBIS模型中的SSN動作原理 19
2.5. 電子網路分析之基礎原理 21
2.5.1. 克西荷夫電流定律 21
2.5.2. △－Y互換法 21
第三章 HFLI增強模組架構設計 23
3.1. 架構概念 23
3.2. 模組原理 23
3.3. 原理分析 26
3.4. HFLI之IBIS建構流程 27
3.4.1. 建立緩衝器模型 27
3.4.2. 參數取得 28
3.4.3. SPICE轉IBIS 29
3.4.4. 接腳與各別模型對應 29
第四章 模擬概念、原理及分析 30
4.1. 模擬概念及電路設定 30
4.2. 模擬原理及電路特徵阻抗 35
4.3. 模擬電路之分析 39
4.3.1. 輸入訊號由High轉態到Low 39
4.3.2. 輸入訊號由Low轉態到High 45
第五章 主要研究結果 48
第六章 結論 55
參考文獻 56
附錄A. 中英對照表 59
附錄B. 發表EI文章： 61
附錄C. 發表SCI文章： 69

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