臺灣博碩士論文加值系統

在這篇論文中，我們提出一個有雙輸出準位的低壓降線性穩壓器。此低壓降線性穩壓器可以透過外部控制訊號加以控制，進而產生兩個不同準位的穩定輸出電壓。本架構適合單一線性穩壓器可以輸出兩種電壓，他們分別是2.5伏特和1伏特，並且很適合應用於電源供應系統中。又因為把兩顆穩壓器作成一顆，所以面積將大幅降低也可以解省成本。除此之外，此架構包含以下單元:具雙輸出準位之參考電壓產生器、動態放電路徑使得高低電壓轉換時間縮短、預防瞬間過大電流的限流器。模擬結果顯示這提出的架構可以在五個狀態角都維持不錯的特性。

In this thesis, we present a dual output voltage levels low drop-out (LDO) linear regulator. The regulator could produce two different output voltage levels for the same output by using an external selection signal. The proposed LDO structure is suitable for a power management system that required more than one supply voltage level with small area. The output voltage levels are 1V and 2.5V in this design. Our proposed dual output voltage level LDO linear regulator consists of a novel two-level reference voltage generator, a fast discharging path for the switching between voltage levels to reduce the settling time, and a current limiter to prevent sudden current overshoot. Simulation results indicate that the proposed design can maintain its performance within bound under five design corners.

Chapter 1 Introduction 1
1.1 Definition 1
1.2 The Demands of Market 2
1.2.1 Current Efficiency, Low Voltage and Low Dropout 2
1.2.2 Alternative: DC-DC Converter/Switching Regulators 3
1.3 Structure Overview of the LDO Linear Regulator 5
1.3.1 General Structure 5
1.3.2 Performance Considerations 6
1.4 Motivation 7
1.5 Our Contributions 9
1.6 Thesis Organization 9
Chapter 2 Fundamentals of Low Dropout Linear Regulator 10
2.1 Structure and Operational Principles in LDO Regulator 10
2.2 Characteristics of the LDO Regulator 12
2.2.1 Dropout Voltage 12
2.2.2 Quiescent Current 14
2.2.3 Power Efficiency 15
2.2.4 Load Regulation 16
2.2.5 Line Regulation 17
2.2.6 Power Supply Rejection Ratio 17
2.2.7 Output Noise 18
2.2.8 Stable Range of ESR 19
2.2.9 Accuracy 20
2.2.10 Power Dissipation 20
2.3 Design Issues of the LDO Linear Regulator 21
2.3.1 Series Pass Element 21
2.3.2 Frequency Response 26
2.3.3 Transient Response 30
2.4 Design Considerations 33
2.4.1 Overall System 33
2.4.2 Reference Circuit 36
Chapter 3 Recent LDO Linear Regulators 37
3.1 The Low-Dropout Voltage Regulator in the Recent Years 37
3.1.1 High PSRR LDO linear regulators 37
3.1.2 Low Quiescent Current LDO linear regulators 38
3.1.3 Low Output Noise LDO linear regulators 38
3.1.4 Fast Transient Response LDO linear regulators 39
3.2 The Classification of Adjustable LDO Linear Regulator 40
3.2.1 All Duplicated Type Adjustable LDO Linear Regulator 40
3.2.2 Half-Duplicated type LDO linear regulators 41
3.2.3 Feedback path type Adjustable LDO linear regulators 42
3.2.4 Adjustable Reference Voltage Generator type LDO linear regulators 43
3.2.5 Summary 45
Chapter 4 Proposed Dual Output Voltage Level Low Dropout Linear Regulator 46
4.1 Structure of Reference Voltage Generators 46
4.2 Proposed Dual Output Voltage Level Reference Voltage Generator 52
4.3 Proposed Discharging Path as Switch VOH to VOL 55
4.4 Current Limiting 59
Chapter 5 Simulation Results 62
5.1 Layout Issues 62
5.2 Simulated Results 64
5.3 Discussions of Simulation Results 79
Chapter 6 Conclusions and Future Works 81
6.1 Conclusions 81
6.2 Future Works 82
References 84
自述 91

[1] S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits. New York: McGraw-Hill Publishing Company, 1988. [2] M.M. Cirovic, Integrated Circuits: A User's Handbook. Reston, Virginia: Reston Publishing Company, Inc., 1977 [3] P.R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: John Wiley & Sons, Inc., 1993. [4] F. Goodenough, “Low Dropout Linear Regulators,” Electronic Design, pp. 65-77, May 13, 1996. [5] T. Regan, “Low Dropout Linear Regulators Improve Automotive And Battery-Powered Systems,” Powerconversion and Intelligent Motion, pp. 65-69, February 1990. [6] J. Wong, “A Low-Noise Low Drop-Out Regulator for Portable Equipment,” Powerconversion and Intelligent Motion, pp. 38-43, May 1990. [7] R. Cavin and W. Liu, Emerging Technologies, Designing Low Power Digital Systems. Piscataway, NJ: Institute of Electrical and Electronics Engineers, 1996. [8] A. Matsuzawa, “Low Voltage Mixed Analog/Digital Circuit Design for Portable Equipment,” 1993 Symposium on VLSI Circuits Digest of Technical Papers, pp. 49-54, 1993. [9] E. Nash, “Take Advantage of Fast Rail-To-Rail Op Amps in low-Voltage Systems,” Electronic Design Analog Applications Issue, pp. 26-39, June 24, 1996. [10] F. Goodenough, “Fast LDOs And Switchers Provide Sub-5-V Power,” ElectronicDesign, vol. 43 #18, pp. 65-74, September 5, 1995.
85
[11] F. Goodenough, “Power-Supply Rails Plummet and Proliferate,” Electronic Design, pp. 51-55, July 24, 1995. [12] K.M. Tham and K. Nagaraj, “A Low Supply Voltage High PSRR Voltage Reference in CMOS Process,” IEEE Journal of Solid-State Circuits, vol. 30 #5, pp. 586-590, May 1995. [13] H. Chung and A. Ioinovici, “Switched-Capacitor-Based DC-toDC Converter with Improved Input Current Waveform,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 541-544, May 1996. [14] G. Zhu and A. Ioinovici, “Switched-Capacitor Power Supplies: DC Voltage Ratio Efficiency, Ripple, Regulation,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 553-556, May 1996. [15] B.D. Moore, “Circuit trade-offs minimize noise in battery-input power supplies,” EDN, pp. 107-112, January 18, 1996. [16] F. Goodenough, “Off-Line and One-Cell IC Converters Up Efficiency,” Electronic Design, pp. 55-64, June 27, 1994. [17] M. Sauerwald, “Keeping Analog Signals Pure In A Hostile Digital World,” Electronic Design Analog Applications Issue, pp. 57-64, June 24, 1994. [18] P.E. Allen and D.R. Holdberg, CMOS Analog Circuit Design. New York: Holt, Rinehart and Winston, 1987. [19] Linear/Switchmode Voltage Regulator Handbook. Fourth edition, 1989. [20] S. J. Jou, and T. L. Chen, “On-chip voltage down converter for low-power digital system,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, Issue 5, pp. 617-625, May 1998.
86
[21] N. L. Ka, P. K. T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation,” IEEE Journal of Solid-State Circuits, Vol. 38, Issue 10, pp. 1691-1702, Oct 2003. [22] R. Tantawy, E. J. Brauer, “Performance evaluation of CMOS low drop-out voltage regulators,” in Proceedings of the 47th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 141-144, Jul. 2004. [23] B. S. Lee, “Understanding the terms and definitions of LDO voltage regulators,” Application Report, Texas Instruments Inc., Oct. 1999. [24] B. S. Lee, “Technique review of Low Dropout Voltage Regulator Operation and Performance,” Application Reports, Texas Instruments Inc., Oct. 1999. [25] M. Tuthill, “A switched-current, switched-capacitor temperature sensor in 0.6μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 33, Issue 7, pp. 1117-1122, Jul. 1998. [26] A. Bakker, K. Thiele, and J. H. Huijsing, “A CMOS nested-chopper instrumentation amplifier with 100nV offset,” IEEE Journal of Solid-State Circuits, Vol. 35, Issue 12, pp. 1877-1883, Dec. 2000. [27] G. C. M. Meijer, J. van Drecht, P. C. de Jong, “New concepts for smart signal processors and their application to PSD displacement transducers,” Sens. Actuators A, Vol. 35, 1992. [28] Sedra and Smith, “Microelectronic Circuit,” Oxford University Pass, Inc., 1998. [29] M. K. Brian, “Advantages of using PMOS-type low-dropout linear regulators in battery applications,” Journal of Analog Applications, Texas Inc., Aug. 2000. [30] C. Simpson, “Linear Regulators: Theory of Operation and Compensation,” National Semiconductor Application Note 1148, May 2000.
87
[31] G. Bontempo, T. Signorelli, and F. Pulvirenti, “Low Supply Voltage, low quiescent current, ULDO linear regulator,” in Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems, Vo1. 1, pp. 409-412, Sept. 2001. [32] E. Rogers, “Stability analysis of low-dropout linear regulators with a PMOS pass element,” Journal of Analog Applications, Texas Instruments Inc., Aug. 1999. [33] R.J. Widlar, “New Developments in IC Voltage Regulators,” IEEE Journal ofSolid-State Circuits, vol. SC-6 #1, pp. 2-7, February 1971. [34] Hoon S.K. et al., “A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications,” IEEE 2005 Custom Integrated Circuits Conference, pp. 759-762, Sept. 2005. [35] Liang-Guo Shen et al., “Design of Low-Voltage Low-Dropout Regulator with Wide-Band High-PSR Characteristic,” Institute of Microelectronics, Peking University, Shen Graduate School, China, 2006. [36] Dongpo Chen et al., “A Low-dropout Regulator with Unconditional Stability and Low Quiescent Current,” Department of Electrical and Electronic Engineering, The Zhejiang University, Hangzhou, Zhejiang, China, 2006. [37] Tsz Yin Man, Philip K. T. Mok, Mansun Chan, “A High Slew-Rate Push-Pull Output Amplifier for Low-Quiescent Current Low-Dropout Regulators With Transient-Response Improvement,” IEEE Trans. Circuits and Systems II, vol. 54, no. 9, pp. 755-759, Sep. 2007. [38] Mannama, V. et al., “Ultra low noise low power LDO design,” Baltic Electronics Conference, 2006 International, pp. 1-4, Oct. 2006. [39] Mohammad Al-Shyoukh et al., “A Transient-Enhanced 20μA- Quiescent 200mA-Load Low-Dropout Regulator With Buffer Impedance Attenuation,” IEEE 2006 Custom Integrated Circuits Conference, pp. 615-618, Sept. 2006.
88
[40] Oh, W.; Bakkaloglu, B., “A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier,” IEEE Trans. Circuits and Systems II, vol. 54, pp. 922-926, Oct. 2007. [41] Bing-You Gau, “Design and Implementation of an Adjustable Low Dropout Voltage Regulator,” Thesis for Master of Science, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C., July 2006. [42] P. M. Alicea-Morales, C. J. Ortiz-Villanueva, R. Pérez, R. Palomera-Garcia, M. Jiménez, “Design of an Adjustable, Low Voltage, Low Dropout Regulator,” in Proceedings of the 5th IEEE International Caracas Conference on Devices, Circuits and Systems, Vol.1, pp. 289-292, Nov. 2004. [43] H. Hu, and Y. Li, “A new on-chip DC-DC voltage down converter for low power VLSI,” in Proceedings of the 4th International Conference on ASIC, pp. 244-247, Oct. 2001. [44] N. L. Ka, and P. K. T. Mok, “A CMOS voltage reference based on weighted △VGS for CMOS Low-Dropout linear regulators,” IEEE Journal of Solid-State Circuits, Vol. 38, Issue 1, pp. 146-150, Jan. 2003. [45] N. L. Ka, and P. K. T. Mok, “A CMOS voltage reference based on weighted difference of gate-source voltages between PMOS and NMOS Transistors for Low-Dropout Linear Regulators,” in Proceedings of the 27th European Solid-State Circuits Conference, pp. 61-64, Sept. 2001. [46] P. R. Gray and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits,” New York: John Wiley & Sons, Inc., Feb. 1989. [47] K. N. Leung and P. K. T. Mok, “A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device,” IEEE Journal of Solid-State Circuit, Vol. 37, pp. 526-530, Apr. 2002.
89
[48] T. Kawahara, T. Kobayashi, Y. Jyouno, S.-I. Sacki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume and K. Kimura, “Bit-Line Clamped Sensing Multiplex and Accurate High Voltage Generator for Quarter-Micron Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 31, pp. 1590-1599, Nov. 1996. [49] Y. P. Tsividis, “Accurate Analysis of Temperature Effects in IC-VBE Characteristics with Application to Bandgap Reference Sources,” IEEE Journal of Solid-States Circuits, Vol. 15, Issue 6, pp. 1076-1084, Dec. 1980. [50] M. Schenkel, P. Pfäffli, S. Mettler, W. Reiner, W. Wilkening, D. Aemmer, and W. Fichtner, “Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection,” in Proceedings of the 30th European Solid-State Device Research Conference, pp. 600-603, Sep. 2000. [51] Song L., Jacob B., “Process and Temperature Performance of a CMOS Beta-Multiplier Voltage Reference,” in Proceedings of Midwest Symposium on Systems and Circuits, pp. 33-36, Aug. 1998. [52] C. Simpson, “Linear Regulators: Theory of Operation and Compensation,” National Semiconductor Application Note 1148, May 2000. [53] LIN Chuan, FENG Quan-yuan, "Design of Current Limiting Circuit in Low Dropout Linear Voltage Regulator," Microwave Conference Proceedings, 2005. APMC, Vol. 2, Dec. 2005. [54] K. N. Leung and P. K. T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1691–1701, Oct. 2003.
90
[55] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S. Borkar, “Area-efficient linear regulator with ultra-fast load regulation,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933–940, Apr. 2005. [56] Robert J. Milliken, Jose Silva-Martinez, Edgar Sanchez-Sinencio, “Full On-Chip CMOS Low-Dropout Voltage Regulator,” IEEE Trans. Circuits and Systems I, vol. 54, no. 9, pp. 1879-1890, Sep. 2007.