臺灣博碩士論文加值系統

　　影像數位化為將影像作分析、儲存、運算及傳播時最有效率的方法。影像感測器是影像數位化的前端系統，目前影像感測元件主要分為電荷耦合元件(CCD)及金氧互補半導體影像感測元件(CMOS)兩種，一般傳統的攝相系統採用CCD影像感測器單頻道類比輸出，再以單顆類比數位轉換器將類比訊號轉換為數位影像訊號；此架構在數位影像資料規格日益龐大的發展趨勢下，是有其速度上的限制；亦不適於應用為機械儀器之視覺系統應用上。相較於CCD，CMOS擁有可集成化之優點，可將周邊電路整合同一晶片上，故逐漸取代CCD成近年來之趨勢。
　　本論文內容提供理論、設計、實作與測試一內含 64 x 64 CMOS APS像素陣列之攝相單晶片系統晶片。本晶片提供由像素端到類比數位轉換器數位輸出之完整途徑，晶片中包含了64 x 64 單顆像素面積8.05 x 8.05 um2之CMOS APS像素陣列、平行相關性雙取樣電路及平行處理12位元類比數位轉換器，周邊電路部分則有參考電壓電路提供四組所需之參考電壓，以及時脈產生器產生控制晶片運作之時脈電路。
　　陣列所擷取之影像經由平行相關性雙取樣電路與平行處理12位元類比數位轉換器後，可得數位化之影像資料，再經由FPGA對每筆資料作重新排序後，便可交由影像擷取卡送至PC顯示圖形，並做後續處理。
　　本攝相單晶片系統晶片採用TSMC 0.18 CMOS RF‐Mix signal 3.3V 1p6m製程，單顆CDS佈局面積2042 um2，單顆ADC佈局面積 11254 um2 ，ENOB大於 11‐bit，全晶片消耗功率小於60 mW，此設計可以提供達HDTV 1080p規格之高畫面更新率，64 x64像素陣列循序掃瞄畫面更新率則達520 Frame/s。

　　Images in digital format is the most effective way for analysis, storage, and operation. The imager is the front-end of any machine vision system. There are two major type imager, Charge Coupled Device (CCD) and Complementary Metal-Oxide Semiconductor (CMOS). In order to achieve the function of digital image output, modern imaging system are typically implement with signal digitization function. For example, a traditional CCD camera system with a single analog output channel can be implemented with an independent single-chip ADC to convert analog image signal to digital format.
　　However, this traditional architecture faces the insufficient frame-rate limitation as high quality, high resolution digital images are required. For some machine vision applications, this architecture cannot achieve the desirable speed. Compared with CCD, the CMOS imager has the advantage of being integrated with CDS, ADC, and other control circuits on a single chip with CMOS process. Therefore the CMOS imager takes the place of CCD imagers step by step.
　　This thesis describes the theory, design, characterization and testing of a prototype 64 x 64 active pixel sensor (APS) array. This chip realizes a system including the pixel array, column-parallel correlated double sampling circuit (CDS) and column-parallel 12-bit analog-to-digital converter (ADC). There are on-chip reference voltage circuit and clock generator providing four reference voltage and all operation signals to control the chip. The array output utilizes the CDS and the ADC to convert image signal to digitized format. After reforming these digitized data with FPGA, we can show these image on PC via the digital frame grabber and make other process.
　　This camera-on-a-chip system uses TSMC 0.18 CMOS RF-Mix signal 3.3V 1p6m process. The layout area of each pixel is 8.05 x 8.05um2. The CDS area and ADC area are 2042 um2 and 11254 um2. The power consumption of the chip is 60 mW with ENOB as high as 11-bit. The CDS and ADC allow a high frame rate that can achieve the HDTV 1080p specification. And the maximum frame rate of the 64 x 64 CMOS image sensor array is 520 frames/s with progressive scan.

第一章　簡介　　1
1.1　　研究動機　　1
1.2　　晶片規格設計　　3
第二章　背景資料　　5
2.1　　CCD及CMOS影像感測器介紹　　5
2.1.1　主動式與被動式感光元件介紹　　7
2.2　　應用於影像感測器之類比數位轉換器型態　　9
2.2.1　雙斜率式(Dual-Slope　Converter)　　10
2.2.2　連續逼近式(Successive　Approximation,　SAR)　　12
2.2.3　遞迴式(cyclic　ADC)　　14
第三章　晶片之架構及設計　　16
3.1　　全晶片架構　　16
3.2　　像素陣列（Pixel　Array）及控制電路　　18
3.2.1　電路架構及運作原理　　18
3.2.2　像素陣列之模擬結果與佈局圖　　19
3.2.3　像素陣列之控制電路　　20
3.2.4　雜訊　　21
3.3　　運算放大器電路及設計　　24
3.3.1　運算放大器之共模迴授電路(Common-Mode　Feedback　Circuits）　　27
3.3.2　運算放大器非理想性分析　　29
3.3.3　任意雜訊　　32
3.3.4　模擬結果　　32
3.4　　相關性雙取樣電路（Correlated　Double　Sampling,　CDS）　　34
3.4.1　電路與運作原理　　35
3.4.2　理想狀態之操作模式分析　　37
3.4.3　相關性雙取樣電路之非理想特性　　38
3.4.4　相關性雙取樣電路運算放大器模擬結果　　44
3.4.5　相關性雙取樣電路模擬結果　　45
3.4.6　相關性雙取樣電路佈局圖　　50
3.5　　遞迴式類比數位轉換器（Cyclic　Analog-to-Digital　Converter)　　51
3.5.1　電路與運作狀態分析　　55
3.5.2　理想狀態之操作模式分析　　58
3.5.3　遞迴式類比數位轉換器之非理想性分析　　59
3.5.4　遞迴式類比數位轉換器之模擬結果　　66
3.5.5　遞迴式類比數位轉換器之佈局圖　　68
3.6　　時脈產生器（Clock　Generator）　　69
3.6.1　邏輯電路　　71
3.7　　晶片佈局與訊號接腳　　74
第四章　晶片量測　　78
4.1　　測試架構　　78
4.2　　測試驗證平台　　79
4.3　　遞迴式類比數位轉換器測試　　81
4.4　　相關性雙取樣電路_遞迴式類比數位轉換器測試　　82
4.5　　單晶片攝相系統測試　　83
4.6　　測試板　　84
第五章　結論　　86
5.1　　論文貢獻　　86
5.2　　未來改進　　86

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