臺灣博碩士論文加值系統

複晶矽薄膜電晶體被廣泛地運用於主動式陣列液晶顯示器，而複晶矽所含的晶界會直接影響臨限電壓的變異。本篇論文主要在於研究晶界位置效應對臨限電壓的影響。於是發展出兩個新的模型：一個是透過二維波以松公式來模擬單一晶界的的模型﹔另一個則是使用拉普拉斯轉換來計算側向表面電位的多晶界模型

Polycrystalline silicon thin film transistors (poly-Si TFTs) are widely used in active matrix liquid crystal displays (AMLCDs). Grain boundaries will cause the variation of threshold voltage in poly-Si TFTs. This thesis focuses on the effect of the locations of grain boundaries on the threshold voltage. New analytical models were developed. Base on the solution by two dimensional Poisson’s equation, lateral surface potential with a single grain boundary was obtain by assuming the grain boundary as a region with trapped charges. La-place transform was calculated to obtain the surface potential with multiple grain boundaries in poly-Si TFTs.

Table of Contents
Abstract iii
Table of Contents iv
List of Figures v
Chapter 1 1
Introduction 1
Chapter 2 6
Modeling of a grain boundary in the channel 6
2.1 Poisson’s equation in the channel region 6
2.2 Single-grain-boundary model 11
2.2.1 Modification of the previous model 11
2.2.2 Threshold voltage 18
Chapter 3 24
Modeling of multiple grain boundaries in the channel 24
Chapter 4 34
Simulation of HSPICE 34
Chapter 5 37
Conclusion 37
Reference 39


List of Figures
Fig 1-1 The flowchart of device modeling from process to circuit simulations 1
Fig 1-2 Gradual channel approximation (GCA) 2
Fig 1-3 The uniform lateral electric field distribution near the drain region 3
Fig 1-4 The linear lateral electric field distribution near the drain region 4
Fig 1-5 (a) Cros-sectional diagram of a pocket n-MOSFET structure and the (b) surface potential profile between drain and source adapted from ref.[6] 4
Fig 1-6 Grain boundary cause barrier height VB by charge trapping 5
Fig 2-1 Definitions of the boundaries of the channel depletion region 7
Fig 2-2 Electric field distribution in the channel depletion region 9
Fig 2-3 Electric field distribution in the channel depletion region 10
Fig 2-4 Definition of the channel regions in the Yu model [5]. 12
Fig 2-5 Result of the modification with electric field continuity 16
Fig 2-6 The process of narrowing the center region 17
Fig 2-7 The result of narrowing the middle region 18
Fig 2-8 The lateral surface potential Vs(x) for different Leff. 22
Fig 2-9 The threshold voltage variation for different Leff 23
Fig 3-1 Cross section of poly-Si TFT with multiple grain boundaries in channel 25
Fig 3-2 Condense the trap doping region to a delta function with dose and uniform doping 26
Fig 3-3 Agreement between single grain boundary model and multiple grain boundary model with L=1um and VDS=0.1V 29
Fig 3-4 Poly-Si TFT with equal distance between adjacent grain boundaries in poly-Si TFT with VDS=3V and Leff=1um 30
Fig 3-5 Poly-Si TFT with equal distance between adjacent grain boundaries for different numbers of grain boundary 31
Fig 3-6 Lateral surface potential distribution in different distance between two grain boundaries 32
Fig 3-7 The relationship between barrier height and distance of two grain boundaries 33
Fig 4-1 Ids-Vgs curves of original RPI and modified RPI model of poly-Si TFT with Vds = 10V in linear scale 34
Fig 4-2 Ids-Vgs curves of original RPI and modified RPI model of poly-Si TFT with Vds = 10V in log scale 35
Fig 4-3 Asymptote of Ids-Vgs curve of modified RPI model for approximate Vth of poly-Si TFT 36


List of Figures
Figure 2.1 Parameter values for Vth derivation 21
Figure 3.1 Laplace transform 26

[1] H.C. Pao, C.T. Sah , “Effects of diffusion current on characteristics of metal oxide semiconductor transistors,” Solid-State Electronics, Vol.9, p927-937, 1966.
[2] Y. A. El-Mansy, A. R. Boothroyd, “A simple Two-Dimensional Model for IGFET Operation in the Saturation Region,” IEEE Trans. on Electron Devices, Vol. ED-24, No. 3, Mar. 1977.
[3] Ping Keung Ko, “Hot-Electron Effects in MOSFETs,” PhD. Thesis, University of California, Berkley, 1982.
[4] Z. Liu, C. Hu, J. Huang and et. al., "Threshold Voltage Model for Deep-Submicrometer MOSFET's," IEEE Transaction on Electron Devices, vol. 40, no. 1, pp. 86-95, Jan. 1993.
[5] B Yu, CHJ Wann, ED Nowak, and et. al, “Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's,” IEEE Trans. on Electron Devices,, Vol. 44, No. 4, Apr. 1997.
[6] Yon-Sup Pang and John R. Brews, “Analytical Subthreshold Surface Potential Model for Pocket n-MOSFETs”, IEEE Trans. on Electron Devices,, Vol. 49, No. 12, Dec. 2002.
[7] John Y. W. Seto, “The electrical properties of polycrystalline silicon films,” Journal of Applied Physics, Vol. 46, Issue 12, 1975.
[8] Baccarani, G., Riccò, B. and Spadini, G., “Transport properties of polycrystalline silicon films, ” Journal of Applied Physics, Vol. 49, Issue 11, pp. 5565-5570, 1978.
[9] J.G. Fossum and A. Ortiz-Conde, “Effects of grain boundaries on the channel conductance of the SOI MOSFET's,” IEEE Trans on Electron Devices, ED-30, pp. 933–940, 1983.
[10] Nicky Chau-Chun Lu, Levy Gerzberg, Chih-Yuan Lu, “An New Conduction Model for Polycrystalline Silicon Films,” IEEE Transaction or Conference, Vol. 2, No. 4, Apr. 1981.
[11] HL Chen and CY Wu, “An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor,” IEEE Trans. on Electron Devices, Vol.45, No. 10, pp.2245-2247, 1998.
[12] P. Lin, J. Guo and C. Wu, “A quasi-two-dimensional analytical model for the turn-on characteristics of polysilicon thin-film transistor,” IEEE Trans. on Electron Devices. Vol. 37, pp. 666–674, 1990.
[13] Silvaco verilog-A RPI model for poly-Si TFT , “https://dynamic.silvaco.com/dynamicweb/silen/”