臺灣博碩士論文加值系統

在此篇論文中，藉由高介電係數材料的引入，探討具氧化鏑(Dy2O3)電荷捕捉層之金氧半結構非揮發性記憶體元件特性研究，並藉由評估遲滯窗口、寫入時間、抹除時間、耐久力及保持力等五項特性獲得最佳氧化鏑電荷捕捉層。首先利用快速熱退火爐搭配不同溫度製作不同的二氧化矽當作金氧半電容記憶體元件之穿遂氧化層，接著探討利用濺鍍機沈積之氧化鏑電荷捕捉層之熱退火特性研究，改變不同沉積後熱退火溫度，獲得最佳氧化鏑電荷捕捉層。接著，為了達到操作更快速與低操作電壓的目的，改變不同阻擋層與氧化鏑電荷捕捉層堆疊厚度比例，改善具氧化鏑電荷捕捉層之金氧半結構的特性；最後利用不同量的白金(Pt)摻雜氧化鏑當做金氧半結構非揮發性記憶體元件之電荷捕捉層。
實驗結果顯示，當二氧化矽穿遂層氧化溫度為900 ℃，同時氧化鏑沉積後熱退火溫度為750 ℃時，其寫入特性較佳。而當二氧化矽/氧化鏑堆疊層為20/15 nm時，其在正負19 V的遲滯可達3.24 V。且從遲滯結果獲得記憶機制為電洞捕捉為主，同時在此組合情況下會有較佳的寫入及抹除特性。此外，在具氧化鏑電荷捕捉層之金氧半結構非揮發性記憶體元件中，以白金摻雜氧化鏑30秒時，其在正負19 V的遲滯增至為11.48 V，且擁有更快的寫入時間且降低操作電壓。

Characteristics of metal-oxide-semiconductor (MOS) structured nonvolatile memory (NVM) devices with various dysprosium oxide (Dy2O3) dielectrics as charge trapping nodes have been presented in this study. The memory characteristics include hysteresis, programming/erasing time, endurance, and retention. First, various tunneling oxides were formed by tuning various rapid thermal annealing (RTA) temperatures. Then, the effects of post-deposition annealing (PDA) on Dy2O3 charge trapping layer of MOS structured NVM were investigated. Furthermore, characteristics of MOS structured NVM devices with various stacked SiO2/Dy2O3 dielectrics as blocking oxide/charge trapping nodes have been also presented. Finally, the effects of Pt-doped Dy2O3 dielectrics as charge trapping layers on characteristics of MOS structured NVM devices were demonstrated.
The results suggest that the better programming time can be demonstrated for the capacitor with the SiO2 tunneling oxide annealing at 900 ℃ and the Dy2O3 trapping layer treated at 750 ℃. Then, capacitance-voltage (C-V) measurements estimate that the memory window of 3.24 V was achieved during the C-V hysteresis sweep at ?19 V. The hysteresis characteristics measurements illustrate that the memory is mainly due to holes trapping. The larger memory window and the better erasing characteristic as well as the better programming characteristic, attributable to the thicker trapping layer (Dy2O3 dielectrics) and the thinner blocking oxide layer (SiO2). Thus, the stacked SiO2/Dy2O3 dielectric of 20/15 nm was demonstrated for MOS nonvolatile memory device applications. Moreover, a larger hysteresis shift of 11.48 V sweep at ±19 V, a faster programming time, and a lower operated voltage can be achieved by the Pt-doped Dy2O3 ¬trapping layer under the sputtering time of 30 s.

目錄
摘要.....i
Abstract.....ii
誌謝.....iii
目錄.....iv
表目錄.....vii
圖目錄.....viii
第一章 緒論.....1
1.1 高介電係數閘極介電層(High-k dielectric)發展概述.....1
1.2 研究動機.....4
1.3 論文架構.....4
第二章 元件製程與量測.....6
2.1 探討不同穿遂層氧化熱處理溫度對具Dy2O3電荷捕捉層之金氧半結構非揮發性記憶體元件特性研究.....6
2.1.1 晶圓處理.....6
2.1.2 穿隧氧化層製程.....7
2.1.3 電荷捕捉層製程.....7
2.1.4 阻擋氧化層製程.....7
2.1.5 上下電極製程 .....7
2.2 探討不同電荷捕捉層沉積後熱處理溫度對具Dy2O3電荷捕捉層之金氧半結構非揮發性記憶體元件特性研究.....8
2.2.1 晶圓處理.....8
2.2.2 穿隧氧化層製程.....8
2.2.3 電荷捕捉層製程.....8
2.2.4 阻擋氧化層製程.....9
2.2.5 上下電極製程 .....9
2.3 探討不同阻擋層與電荷捕捉層堆疊厚度比例對具Dy2O3電荷捕捉層之金氧半結構非揮發性記憶體元件特性研究.....9
2.3.1 晶圓處理.....9
2.3.2 穿隧氧化層製程.....10
2.3.3 電荷捕捉層製程.....10
2.3.4 阻擋氧化層製程.....10
2.3.5 上下電極製程 .....10
2.4 探討不同量的白金摻雜對具Dy2O3電荷捕捉層之金氧半結構非揮發性記憶體元件特性研究.....10
2.4.1 晶圓處理.....11
2.4.2 穿隧氧化層製程.....11
2.4.3 電荷捕捉層製程.....11
2.4.4 阻擋氧化層製程.....11
2.4.5 上下電極製程 .....12
2.5 電性及可靠度量測方法.....12
2.5.1 遲滯(Hysteresis)特性量測.....12
2.5.2 寫入時間(Programming Times)特性量測.....12
2.5.3 抹除時間(Erasing Times)特性量測.....12
2.5.4 耐久力(Endurance)特性量測.....13
2.5.5 保持力(Retention)特性量測.....13
第三章 具氧化鏑電荷捕捉層之金氧半結構非揮發性記憶體元件特性研究.....26
3.1 探討不同穿遂層氧化熱處理溫度對具Dy2O3電荷捕捉層之金氧半結構非揮發性記憶體元件特性研究.....26
3.1.1 遲滯特性(Hysteresis).....26
3.1.2 寫入時間特性(Programming Times).....27
3.1.3 抹除時間特性(Erasing Times).....27
3.1.4 耐久力特性(Endurance, P/E cycles).....27
3.1.5 保持力特性(Retention).....27
3.1.6 結論.....28
3.2 探討不同電荷捕捉層沉積後熱處理溫度對具Dy2O3電荷捕捉層之非揮發性記憶體元件特性研究.....28
3.2.1 遲滯特性(Hysteresis).....28
3.2.2 寫入時間特性(Programming Times).....28
3.2.3 抹除時間特性(Erasing Times).....29
3.2.4 耐久力特性(Endurance, P/E cycles).....29
3.2.5 保持力特性(Retention).....29
3.2.6 結論.....30
3.3 探討不同阻擋層與電荷捕捉層堆疊厚度比例對具Dy2O3電荷捕捉層之非揮發性記憶體元件特性研究.....30
3.3.1 遲滯特性(Hysteresis).....30
3.3.2 寫入時間特性(Programming Times).....30
3.3.3 抹除時間特性(Erasing Times).....31
3.3.4 耐久力特性(Endurance, P/E cycles).....31
3.3.5 保持力特性(Retention).....32
3.3.6 結論.....32
3.4 探討不同量的白金摻雜對具Dy2O3電荷捕捉層之非揮發性記憶體元件特性研究.....32
3.4.1 遲滯特性(Hysteresis).....32
3.4.2 寫入時間特性(Programming Times).....33
3.4.3 抹除時間特性(Erasing Times).....33
3.4.4 耐久力特性(Endurance, P/E cycles).....33
3.4.5 保持力特性(Retention).....34
3.4.6 結論.....34
第四章 總結與建議.....82
4.1總結.....82
4.2建議.....82
參考文獻.....83
英文論文大綱
作者簡歷

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