臺灣博碩士論文加值系統

這篇論文首先提出了一個用來分析雙向性穿隧或型快閃記憶體操作特性的方法，雙向性穿隧或型快閃記憶體指的是在傳統的或型快閃記憶體中加入一個獨立淺P型井的結構，使之能利用雙向性富爾諾罕穿隧效應達到編程及抹除的操作，如此非但可以減低功率消耗，更可以增進元件的可靠度，同時保留快速隨機存取的優點。藉由理論分析，元件的三度空間效應得以完整考量，同時可以解讀每一項元件及製程參數對操作特性的影響。利用理論推導結果設計出來的遞增電壓波形操作模式，可以有效降低操作電場、提高操作效率、增進元件可靠度，並能準確控制元件被編程後的臨界電壓。從實際元件的量測結果也證實了元件被編程後的臨界電壓分佈確實十分集中。除此之外，這篇論文也提出了四種不同的操作條件來實現多階層編程操作，用以提高記憶體的儲存密度。其中利用在位元線上施加不同的電壓可以得到簡單有效率的多階層編程操作，而且不需要複雜的週邊線路設計。再者，利用本論文中所提出的漸次變化閘極氧化層技術搭配濃度較淡的源極結構，能夠有效解決雙向性穿隧或型快閃記憶體在進行編程操作時所遭遇到的干擾問題，並且不影響元件編程效率。最後，利用三重井結構可以達到降低抹除操作電壓的目的，並且簡化週邊高壓線路設計及縮小所需的晶片面積。

In this study, a performance analysis methodology is first proposed for BiNOR flash memory. The BiNOR flash memory means that the bi-directional Fowler-Nordheim tunneling effect is adopted for programming/erasing operations in a NOR-type array configuration. With the bi-directional channel Fowler-Nordheim tunneling operations, power consumption can be tremendously reduced, and the cell reliability can be greatly enhanced. With the NOR-type array configuration, fast random access can be achieved. Through device modeling, the impact of the device dimensions and the process parameters on the device characteristics can be comprehensively investigated. Based on the theoretical deductions, a ramped pulse programming method is proposed to achieve the linear programming characteristics. The electric field during operation can be effectively reduced to improve the cell reliability. The self-convergent behavior helps controlling the programmed threshold voltage accurately. Experimental results also demonstrate a tightened threshold voltage distribution. Several schemes based on the ramped pulse programming are presented to achieve multi-level operations. Wherein, a ramped pulse programming method with different bit line voltages is the most promising candidate for multi-level charge storage with minimum circuit overhead. Besides, a graded gate oxide technology combined with a lightly doped source line structure is proposed for eliminating the programming disturbance without degrading the performance. Finally, a triple well isolation is adopted for applying a negative source voltage to reduce the erasing voltage. The peripheral high voltage circuits can thus be simplified and the overall chip area is reduced.

封面
Abstract
Acknowledgements
List of Contents
List of Figures
List of Tables
Chapter I Introduction
Chapter 2 Review of the BiNOR Technology and Related Reliability Issues
2.l A Bi-Directional Tunneling NOR-type (BiNOR) Flash Memory Cell
2.2 Reliability Considerations and Obstacles to a BiNOR Flash Memory
2.2.1 Program/Erase Cycling Endurance
2.2.2 Over-Programmed Problems
2.2.3 Disturb Mechanisms
2.2.3.1 Word Line Disturbance
2.2.3.2 Bit Line Disturbance
2.2.4 Compatibility with the Single Power Supply
Chapter 3 Optimal Design for Programming a BiNOR Flash Memory Cell
3.1 Drawbacks of the Conventional Constant Voltage Operation
3.2 The Constant Field Programming Method
3.2.1 Equivalent Capacitance Model
3.2.2 Coupling Ratio Enhancement
3.2.3 Constant Field Programming Characteristics
3.2.3.1 Deduction of the Threshold Voltage Shift during Programming
3.2.3.2 The Linear Programming
3.2.3.3 Linearly Ramped Word Line Voltage
3.3 Operating Pulse Design
3.3.1 Staircase-Like Ramped Pulse on the Word Line
3.3.2 Self-Convergent Behavior with Different Initial Threshold Voltages
3.3.3 The Tttreshold Voltage Distribution
3.3.4 Impacts of Device Dimensions
3.3.5 Impacts of Process Variations
3.4 Multi-level Charge Storage
3.4.1 The Time Controlled Multi-level Programming
3.4.3 The Word Line Controlled Multi-level Programming
3.4.3 Tile Bit Line Controlled Multi-level Programming
Chapter 4 Disturbance-Free Device Design
4.1 Tile Source Charging Enhanced Gate (SCEG) Disturbance
4.2 Graded Gate Oxide (GGO) Technology
4.2.3 Evaluated Results with the GGO Technology
4.2.3 Tile GGO Technology Combined with the LDS Structure...
4.3 Thc Bit Line Disturbance
Chapter 5 Low Voltage Erasing Operation
5.1 The Drawbacks of the Original Erasing Operation
5.2 Reduction ofthe Erasing Voltage
Chapter 6 Summary and Conclusions
References
Appendix
Vita

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