臺灣博碩士論文加值系統

在此篇論文中，針對" 10Mbps PPM紅外線通訊系統"，設計一個應用於此紅外線系統接收前端的自動增益系統，而此自動增益系統中還包含一個帶通濾波器。
在比較各種不同增益控制系統之後，對於增益系統的架構的選擇，因紅外線通訊系統的速度和穩定性的考量，決定利用迴授（Feedback）雙迴路(Dual Loop)的類比設計來完成此自動增益系統。此自動增益系統不但使得整個控制迴路有較快的收斂速度，也可使整個控制迴路有較穩定的收斂結果。
而帶通濾波器的設計，依照紅外線通訊系統的通道特性（也就是環境的特性），此濾波器的頻段是從1M到10M，在如此寬的頻寬下希望得到較好的訊號特性，帶通濾波器是由一個2級Bessel高通濾波器和一個2級Bessel低通濾波器串聯而成的4級帶通濾波器。
最後，整個自動增益系統所有的線路皆以佈局後的模擬結果驗證無誤。在3.3V下，以台灣積體電路公司SPTM 0.6um金氧半場效應電晶體製程設計，功率消耗共計40mW，晶片面積約佔1.8mm^2。

In this thesis, the 10Mbps PPM infrared (IR) communication system is introduced, and
implemented the analog front-end for the IR communication. The analog front-end
consists of a magnitude control circuit and a 4th-order Bessel bandpass filter.
Various configurations of the magnitude control mechanisms are discussed and compared
on view of the IR communication system. The proposed dual loop AGC provides a wide loop
bandwidth at the initial acquisition-state and a narrow loop bandwidth at the steady-state. Since
the receiver absorbs all the optical signals which includes extra noises comes from the air, the system
would have a banpass filter to strain out the other optical interference sources that is induced
from the external environment and the internal high order harmonics. The 4th-order Bessel bandpass
filter is designed with 5.5 MHz central frequency and 10 MHz bandwidth. The achievement is based on
a second-order high pass filter and second-order low pass filter.
Finally, the overall circuits are verified from post-layout simulation using TSMC
0.6um SPTM CMOS digital technology. The circuits consume 88mW(include driving
buffer) at 10MHz input signal, and the chip area is 1.8 mm^2.

1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 10Mbps PPM IR Communication System 3
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Transceiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3.1 4-ary PPM Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3.2 Channel Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.3 Recevied Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 The Analog Front-End For High Speed IR Communication 11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 The Bandpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 The Magnitude Control Circuits . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1 Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.2 Feed-Forward Type AGC . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.3 Feedback Type AGC . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 The Proposed AGC For IR communication System . . . . . . . . . . . . 14
3.4.1 Doul Loop AGC Architecture . . . . . . . . . . . . . . . . . . . . 15
3.4.2 Doul Loop AGC Mathematics Analysis . . . . . . . . . . . . . . . 18
4 4th-order Bessel Bandpass Filter 22
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 OTA(Operational Transconductance Amplifier) Active Filter . . . . . . . 22
4.3 4th-order Bessel Bandpass Filter Circuit Design . . . . . . . . . . . . . . 23
4.3.1 2ed-order Bessel High Pass Filter . . . . . . . . . . . . . . . . . . 24
4.3.2 2ed-order Bessel Low Pass Filter . . . . . . . . . . . . . . . . . . 26
4.3.3 4th-order Bessel Bandpass Filter Layout and Performance Summary 26
5 The Analog Front-End Integration 33
5.1 The Doul Loop AGC Circuits Design and Simulations . . . . . . . . . . . 33
5.1.1 Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.2 Gain and Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1.3 Recitifer and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . 44
5.1.4 The Switch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2 The Overall Function Circuit Integration . . . . . . . . . . . . . . . . . . 46
5.3 Performance Summary and Layout . . . . . . . . . . . . . . . . . . . . . 47
6 Conclusions 58
A Testing Considerations 59
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