臺灣博碩士論文加值系統

隨著電子產品高功能需求，電子構裝技術朝高密度、輕薄及微小化發展乃一必然趨勢。當製程微縮後，動態隨機存取記憶體(dynamic random access memory，DRAM)晶片中相對應之線路亦需縮小，導線與介電層間常因而產生電阻電容遲滯(RC delay)效應。一般常採用銅/低介電常數材料(Cu/Low-k)改善此問題，但也造成結構強度下降以及導線層與介電層之間黏著性不佳的問題，使得結構於製程中易發生脫層破壞(delamination)等問題，值得吾人深入研究。
本論文主要以ANSYS®有限單元套裝軟體分析DRAM晶片於打線接合(wire bonding)過程及熱循環測試(thermal cycling test)中，導線/介電層墊片(Pad)相關結構在溫度及機械負載下之熱機械行為。此研究分為兩部分：(1)首先針對X公司現有導線/介電層Pad結構，進行三維廣域-局部(global-local)有限單元分析，並對不同銅/低介電常數材料及幾何參數之影響深入評估；及(2)針對不同分布設計之導孔陣列(via array)結構，進行抵抗打線破壞能力之三維有限單元分析，進而探討其幾何寬度對結構強度之影響。
由分析結果顯示，X公司DRAM晶片導線/介電層Pad結構在選定之熱循環測試溫度效應及打線接合條件下尚無問題。在Cu/Low-k材料選擇上，則可考慮以氟矽玻璃(fluorinated silicate glass，FSG)做為Low-k材料。此外，經參數化分析，在熱循環測試溫度效應下，增加Via結構C2層厚度，將有助於Via結構應力的降低；另在打線負載下，增加Via結構C2層和M2層厚度，亦有降低Via結構應力效果。
至於對不同導孔陣列結構分析結果顯示，以插栓棋盤式在抵抗打線破壞能力上最好。而由其參數化分析，當Via結構C2層寬度為M1層金屬寬度的0.5倍，或C1層寬度為M1層金屬寬度的0.5到0.75倍，將有助於導孔陣列結構應力之降低。
本論文上述獲得之結果，將有助於對DRAM晶片疊層結構於打線接合過程及熱循環測試時熱機械行為之瞭解，而進一步參數化分析所獲得之結果，將可提供業者設計時之參考。

With the increase of need for high-function electronic devices such as DRAM chip, electronic devices are being pushed towards high density, lightweight and miniaturization. To attain the goal, a fine circuit rule and high speed device are generally required. As the line space and width of IC interconnect continue decreasing, the parasitic capacitance and resistance of devices would correspondingly increase and, unfortunately, result in the increase of RC delay. It can be however improved by using copper (Cu) metallization and low dielectric materials. However, in spite of the advantages of enhancing electrical performance, the Cu/Low-k layer results in softer mechanical response and weaker adhesion. This can cause interfacial delamination in the interconnect structure of DRAM chip. These problems of DRAM chip in this research work worth further study.
This work mainly discusses thermal-mechanical analysis of metal/dielectric pad structure in DRAM chip in the process of wire bonding and thermal cycling test with ANSYS® program. Firstly, the three-dimensional global-local finite element method is used to analyze metal/dielectric pad structure offered by X company, and to evaluate the effect of different low-k materials on stress in Cu/Low-k interconnect and different metal/dielectric layer thickness. Secondly, according to different layout design of via array structures, analyze how to improve the pad reliability in the process of wire bonding, and further analyze what the width of via array structure has influence on structure stress.
According to the results, the metal/dielectric pad structure in DRAM chip offered by X company does not have any thermal-mechanical trouble in the process of thermal cycling test and wire bonding. In Cu/Low-k interconnection, FSG is the better Low-k material to choose. Through parametric analysis, increasing C2 layer thickness contributes to decrease stress of via structure in the process of thermal cycling test. Increasing C2 and M2 layer thickness also contributes to decrease stress of via structure in the process of wire bonding.
Based on the analysis of layout design of via array structures, “plug-chessboard” via array structure is the better one to choose. Through parametric analysis of “plug-chessboard” via array structure, it is helpful to decrease stress when the width of metal material of C2 layer is 0.5 times of M1 layer, or metal material of C1 layer is 0.5 ~ 0.75 times of M1 layer.
The results achieved in this work can not only help us to understand the thermal-mechanical behavior of metal/dielectric pad structure in DRAM chip during thermal cycling test and wire bonding process, but also offer an initial design stage for electronic packaging industry.

摘要.....................................I
目錄.....................................V
表目錄.................................VII
圖目錄................................VIII
第一章、導論.............................1
第二章、熱循環測試 .......................4
第三章、打線接合技術.....................5
3.1 熱壓接合............................5
3.2 墊片接合強度量測實驗................6
第四章、導線/介電層墊片結構分析..........8
4.1 等效材料常數計算....................8
4.2 三維廣域-局部有限單元分析...........9
第五章、導孔陣列結構分析................12
5.1 導孔陣列結構設計...................12
5.2 三維有限單元分析...................13
第六章、結果與討論 ......................15
6.1 導線/介電層墊片結構................15
6.1.1 熱循環測試溫度效應...............15
6.1.2 打線接合.........................16
6.1.3 銅/低介電常數材料選擇............17
6.1.4 參數化分析.......................19
6.2 導孔陣列結構.......................21
6.2.1 拉力測試實驗驗證.................21
6.2.2 打線接合.........................22
6.2.3 參數化分析.......................23
第七章、結論與未來展望..................26
參考文獻................................30

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