臺灣博碩士論文加值系統

在無線通訊系統中，頻率合成器是用來做訊號頻率的升降之用。在頻率合成器電路裡，壓控振盪器與除頻器是重要的核心電路之ㄧ。對壓控振盪器而言，必須提供低相位雜訊的輸出，以避免相鄰雜訊訊號經由混波轉換產生干擾。而振盪器的輸出則經由除頻器來達成降頻的工作，因此，除頻器需具有高頻操作、寬的操作頻寬及低功率消耗。
第一部分，呈現一個考畢茲電磁耦合自製共振腔壓控振盪器，共振腔以無電感方式憑藉著電磁耦合繞線，自製共振腔為開放式五層環型九十度相位延遲。完成於台積電零點一八微米製程，此供應電壓1.8V，功率消耗為5.76mW，應用在0.7GHz(特高頻頻帶-適用在雷達通訊系統)。晶片面積為1.2*1.2 mm2。
第二部分，首先，我們呈現極寬操作頻帶注入鎖定除三除頻器，完成於台積電矽鍺零點一八微米製程，電路基頻調變區間為3.78GHz至4.32GHz，藉由可變電容調變。此供應電壓1.2V，功率消耗為8.328mW。電路的可調範圍為6.95至8.82 GHz，在注入0dBm功率時，其百分比為23.71%。而除三除頻鎖定操作範圍從6.4GHz至9.25 GHz，其百分比為36.42%。晶片面積為0.93*1.19 mm2 。再以同一顆晶片做注入鎖定除頻器上的電晶體熱載子效應，將電晶體集極、基極掛載加壓電壓為2 V，再做數據分析，其量測時間為20分鐘、40分鐘、60分鐘、120分鐘。量測結果顯示，隨加壓時間的增加，頻帶的鎖定範圍會變小，且基頻頻帶頻率會上升。
第三部分，呈現以C類交叉對共振腔震盪器，實現極寬操作頻帶注入鎖定除頻器，完成於台積電零點一八微米製程，此供應電壓1.8V，功率消耗為10.7mW。電路的可調頻帶操作範圍為10.5至15.3 GHz，在注入0dBm功率時，其百分比為37.21% 。而除三除頻鎖定操作範圍從12GHz至15.3 GHz ，其百分比為24.17%，在注入0dBm功率時。晶片面積為1.2*0.7 mm2 。
最後，呈現極寬操作頻帶注入鎖定除三除頻器，注入端分別以n-type及p-type MOSFET來實現，完成於台積電矽鍺零點一八微米製程，n-type電路除頻範圍區間為9.2GHz至13.4GHz，在注入0dBm功率時，其百分比約為37.17%。此供應電壓0.9V，功率消耗為10.2mW。p-type電路除頻範圍區間為8.4GHz至10.8GHz，在注入0dBm功率時，其百分比約為25%。此供應電壓0.9V，功率消耗為15.3mW。晶片面積為0.825*0.52 mm2 。

The important blocks in the phase locked loop (PLL) are the voltage controlled oscillator (VCO) and the divider circuit. The most power consumption of PLL consumes in VCO and divider. The VCO is requested a low phase-noise to avoid corrupting the mixer-converted signal by close interfering tones for VCO circuit, and the Figure of Merit (FOM) of VCO can be determined by it’s performance.
Firstly, this thesis designs complementary Colpitts voltage controlled oscillator, A 0.7GHz Colpitts oscillator is designed and implemented in a 0.18μm CMOS 1P6M process. It consists of a Colpitts negative resistance cell and an open square loop resonator. At the supply voltage of 1.8 V, the output phase noise of the oscillator is -86.28 dBc/Hz at 1MHz offset frequency from the carrier frequency of 0.7 GHz(Using in UHF Band). The FOM(figure of merit) is -135.57dBc/Hz. Total oscillator core power consumption is 5.76 mW.
Secondly, a new wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm BiCMOS process is presented. The ILFD uses a cross-coupled nMOSFET oscillator with an HBT tail and it also use two HBT injection SiGe HBTs. The injection HBTs serve as harmonic and nonlinear mixers. The core power consumption of the ILFD core is 8.328 mW. The divider’s free-running frequency is tunable from 4.32 to 3.78 GHz by tuning the varactor’s control bias, and at the incident power of 0 dBm. The maximum locking range is 1.87 GHz (23.71%), The incident frequency from 6.95 to 8.82 GHz. The operation range is 2.85 GHz (36.42%), from 6.4 to 9.25 GHz. In addition, the ILFD uses a cross-coupled nMOSFET oscillator with an HBT tail and it also use two HBT injection SiGe HBTs. The effect of hot-carrier stressed injection HBTs on the performance of the ILFD is studied. The stress induces the shift in oscillation frequency, phase noise and HBT output characteristics. It is found the locking range decreases with stress time at fixed dc injection base-emitter bias.
Thirdly , a new wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD is based on a class-C capacitive cross-coupled oscillator. By changing the dc gate bias of cross-coupled transistors to below the dc drain voltage, the locking range of ILFD has been improved. At the supply voltage of 1.8 V, the core power consumption of the ILFD core is 10.7 mW. The incident power of 0 dBm the divider’s maximum locking range is 3.3 GHz (24.17%),with the incident frequency from 12 to 15.3 GHz. At incident power of 0 dBm the divider’s operation range is 4.8 GHz (35.2%), from the incident frequency 10.5 to 15.3 GHz.
Finally ,a wide locking range divide-by-3 injection-locked frequency dividers (ILFDs) using a standard 0.18 μm CMOS process are presented. The ILFDs are based on a cross-coupled n-core MOS LC-tank oscillator with either injection NMOSFETs or pMOSFETs. The core power consumption of the ILFD core with injection nMOSFETs is 10.8 mW at the supply voltage of 0.9V and with circuit core current of 12mA. At the incident power of 0 dBm the maximum locking range is 4.2 GHz (37.17%), from the incident frequency 9.2 to 13.4 GHz. The core power consumption of the ILFD core with injection pMOSFETs is 13.77 mW at the supply voltage of 0.9V and with circuit core current of 15.3mA. At the incident power of 0 dBm the maximum locking range is 2.4 GHz (25%), from the incident frequency 8.4 to 10.8 GHz.

中文摘要 I
Abstract III
誌謝 V
Table of Contents VI
List of Figures VIII
List of Tables XI
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 4
Capter 2 verview of the Voltage-Controlled Oscillators 6
2.1 Introduction 6
2.2 Basic Theory of Oscillators 7
2.3 Classification of Oscillators 11
2.3.1 LC-Tank Oscillator 11
2.3.2 Ring Oscillator 15
2.4 Transformer and Varactor Design in VCO 17
2.4.1 Transformer 17
2.4.2 Capacitor 25
2.4.3 Varactor Design 26
2.4.4 Resistors 30
2.5 Important Parameters of VCO 31
2.5.1 Phase Noise 31
2.5.2 Tuning Range 34
2.5.3 RF Frequency [dBc/Hz]： 35
2.5.4 RF Power [Hz]： 35
2.5.5 Figure of Merit [dBm]： 35
2.5.6 Tuning Sensitivity [Hz/V]： 36
2.5.7 Harmonic/spurious [dBc]： 37
2.5.8 Power Dissipation [mW]： 37
2.5.9 Quality Factor: 37
Chapter 3 Design of Injection Locked Frequency Divider 40
3.1 Principle of Injection Locked Frequency Divider 41
3.1.1 Locking Range 43
3.2 ILFD 45

Chapter 4 Design Oscillator Using Square Open Loop Multiple Split-Ring Resonator 47
4.1 Introduction 47
4.2 Circuit Design 48
4.3 Measurement Results 49
Chapter 5 A Wide-Locking Range ÷3 BiCMOS Injection-Locked Frequency Divider 52
5.1 Wide-Locking Range ÷3 BiCMOS Injection-Locked Frequency Divider 52
5.1.1 Introduction 52
5.1.2 Circuit Design 53
5.1.3 Measurement Results 55
5.2 Hot-carrier Stress Study on ÷3 BiCMOS Injection-Locked Frequency Divider with Injection HBT 59
5.2.1 Introduction 59
5.2.2 Circuit Design 60
5.2.3 Measurement Results 60
Chapter 6 A Low Voltage Wide-Locking Range ÷3
Injection-Locked Frequency Divider 68
6.1 Introduction 68
6.2 Circuit Design 69
6.3 Measurement Results 70
Chapter 7 A Low Voltage Wide-Locking Range ÷3
Injection-Locked Frequency Divider 75
7.1 Introduction 75
7.2 Circuit Design 76
7.3 Measurement Results 78

Chapter 8 Conclusion 83

References 86

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