臺灣博碩士論文加值系統

隨著電子產品越來越多，低功率的設計也持續推陳出新，常被用於當嵌入式記憶體的靜態隨機存取記憶體(Static Random Access Memory, SRAM)的設計也就極為重要。本論文目的為設計出低功耗且面積小的二十八奈米製程下的次臨界電壓靜態隨機存取記憶。
首先將會敘述在二十八奈米製程下的次臨界電壓搭配交錯位元儲存架構靜態隨機存取記憶體現在的趨勢以及會面臨的設計考驗，並且以一套記憶體細胞元設計方法來設計該靜態隨機存取記憶體的記憶體細胞元。最後在只有一種電壓源和一種時脈訊號源的情況下，條列出所有記憶體細胞元實現在次臨界電壓下需要搭配的周邊元件，選出本論文認為最適合的記憶體細胞元實現二十八奈米製程下的次臨界電壓搭配交錯位元儲存架構靜態隨機存取記憶體—dCA10T。
接著探討dCA10T記憶體細胞元依照先前論文所設計出的靜態隨機存取記憶體操作在次臨界電壓下的困難點，利用改變寫入字元線架構換取較小的記憶體細胞元面積，再以搭配自我感測開啟的負位元寫入機制換取升壓電路及電容的面積，最後利用邏輯開關改善虛地在讀取時不必要的功率消耗，完成低功耗且面積面積又小的次臨界電壓交錯位元儲存架構靜態隨機存取記憶體。

誌謝 i
摘要 iv
目錄 v
圖目錄 vii
表目錄 x
第一章 序論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文大綱 5
第二章 次臨界電壓靜態隨機存取記憶體之發展 7
2.1 靜態隨機存取記憶體細胞元設計 7
2.1.1傳統6T細胞元設計 7
2.1.2 低電壓細胞元設計之沿革 12
2.2 二十八奈米製程下的設計困難 16
電晶體電流特性所造成的影響 17
第三章 交錯位元儲存架構 10T靜態隨機存取記憶體細胞元設計 22
3.1 dCA10T 22
3.1.1 dCA10T記憶體細胞元設計背景 22
3.1.2 dCA10T記憶體細胞元設計方法 24
3.2 PNN10T 31
3.2.1 PNN10T記憶體細胞元設計背景 31
3.2.2 PNN10T記憶體細胞元設計方法 32
3.3 Schmitt Trigger Based 10T 36
3.3.1 ST10T記憶體細胞元設計背景 36
3.3.2 ST10T記憶體細胞元設計方法 37
3.4 記憶體細胞元綜合比較 41
第四章 原先版dCA10T靜態隨機存取記憶體電路設計 44
4.1 讀寫分離機制的記憶體細胞元 44
4.2 分列寫入能力並提升軟錯誤抵抗力 45
4.3 交錯對接電壓開關邏輯 47
4.4 利用電晶體堆疊技術增加保持靜態雜訊容忍度 52
4.5 原先版dCA10T靜態隨機記憶體優缺點分析 54
優點 54
缺點 54
第五章 Proposed dCA10T靜態隨機記憶體設計 56
5.1 縮小記憶體細胞元面積 56
5.2 以負位元線寫入取代升壓機制 61
5.3 結合行解碼器減少讀取時虛地放電電流 66
第六章 綜合比較 67
第七章 總結與未來研究方向 71
參考文獻 72

[1]S. R. Nassif, “Modeling and analysis of manufacturing variations,” in Proc. IEEE Conf. Custom Integr. Circuits, 2001, pp. 223-228.
[2]C. Visweswariah, “Death, Taxes and failing chips,” in Proc. Des. Autom. Conf., 2003, pp. 343-347.
[3]S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter variation and impact on circuits and microarchitecture,” in Proc. Des. Autom. Conf., 2003, pp. 338-342.
[4]A. Bhavnagarwala, X. Tang, and J. Meindl, “The impact of intrinsic device fluctuations on CMOS SRAM cell stability,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
[5]X. Tang, V. De, and J. Meindl, “Intrinsic MOSFET parameter fluctuations due to random dopant placement,” IEEE Trans. Very Large Scale Integr. Syst., vol. 5, no. 4, pp. 369-376, Dec. 1997.
[6]S. Mukhopadhyay, H. Mahmoodi, K. Roy, “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 12, pp. 1859-1880, Dec. 2005
[7]D.E. Khalil, M. Khellah, Nam-Sung Kim, Y. Ismail, T. Karnik, V.K. De, “Accurate estimation of SRAM dynamic stability,” IEEE Trans. Very Large Scale Integr. Syst., vol. 16, no. 12, pp. 1639-1647, Dec. 2008
[8] H. Soeleman, and K. Roy, “Ultra-low power digital subthreshold logic circuits,” in proc. VLSI Circuit Symp., 1999, pp. 94-96.
[9] M. E. Hwang, A. Raychowdhury, K. Kim, and K. Roy, “A 85mV 40nW process-tolerant subthreshold 8x8 FIR filter in 130nm technology,” in proc. VLSI Circuit Symp., 2007, pp. 154-155.
[10] B. Zhai, et al., “Energy-efficient Subthreshold processor design,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 8, pp. 1127-1137, Aug. 2009.
[11] A. Wang, and A. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.
[12] D. Bol, R. Ambroise, D. Flandre, and J. D. Legat, “Impact of technology scaling on digital subthreshold circuits,” in proc. ISVLSI, 2008, pp. 179-184.
[13] B. H. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and sizing for minimum energy operation in subthreshold circuits,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, Sep. 2005.
[14]J. P. Kulkarni, K. Kim, and K. Roy, “A 160mV, fully differential, robust Schmitt trigger based sub-threshold SRAM,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007.
[15]I. J. Chang, J. Kim, S. P. Park, and K. Roy, “A 32 kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS,” in Proc. ISSCC, 2008, pp. 388-622.
[16]T. H. Kim, J. Liu, and C. H. Kim, “A voltage scalable 0.26V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode,” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1785-1795, Jun. 2009.
[17]M. Qazl, K. Stawiasz, L. Chang, and K.Roy, “A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS,” in proc. ISSCC, 2010, pp. 350-351.
[18]C. H. Lo, S. Y. Huang, “P-P-N based 10T SRAM cell for low-leakage and resilient subthreshold operation,” IEEE J. of Solid-State Circuits, vol. 46, no. 3, pp. 695-704, Mar. 2011.
[19] A. Teman, L. Pergament, O. Cohen, and A. Fish, “A 250mV 8kb 40nm ultra-low power 9T supply feedback SRAM (SF-SRAM),” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2713-2726, Nov. 2011.
[20]M. F. Chang, et al., “A differential data aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1234-1245, Jun. 2010.
[21] M. Yamauchi, et al., “A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist,” in proc. VLSI Circuit Symp., 2009, pp.158-159.
[22] S. Yoshimoto, et al., ”A 40-nm 0.5-V 20.1-uW/MHz 8T SRAM with low-energy disturb mitigation scheme,” in proc. VLSI Circuit Symp., 2011, pp. 72-73.
[23]E. Seevinck, F. J. List, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,” IEEE J. Solid-State Circuits, vol. sc-22, no. 5, pp. 748-754, Oct. 1987.
[24]J. P. Kulkarni, and K. Roy, “Ultralow-voltage process-variation-tolerant schmitt-trigger-based SRAM design,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., pp. 319-332, 2010.
[25]P. Hamcha, et al., “Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-pm to 90-nm generation,” in proc. IEDM, 2003, pp. 21.5.1-21.5.4.
[26]H. Yamauchi, “A discussion on SRAM circuit design trend in deeper nanometer-scale technologies,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 5, pp. 763-774, May 2010
[27]B. H. Calhoun, A. Wang, and A. Chandrakasan, “A 256kb sub-threshold SRAM in 65nm CMOS,” in proc. ISSCC, 2006, pp. 2592-2601.
[28]Prabhat, D. Flynn ARM, Cambridge, United Kingdom “An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications” .