臺灣博碩士論文加值系統

隨著科技的進步，正交分頻多工(OFDM)的傳輸技術在無線通訊系統中越來越受學界和業界的矚目。由於OFDM的技術有適合長距離傳輸的特性，在許多新一代的通訊系統中都已經採用以OFDM的技術做為傳輸的主軸，如 WiMAX、DVB、WLAN等等。其實OFDM在較早的年代就已經有人提出，不過礙於子載波產生虛耗費龐大硬體故無法以低成本的方式實現，直到FFT(快速傅立葉轉換)的架構被人提出之後OFDM有了新的契機。為了支援傳統分碼多重擷取系統(CDMA)，正交分頻多工存取技術(OFDMA)的技術也早已被提出和討論，如今OFDMA已成為4G產品的熱門技術，因此，IEEE 802.16組織在去年底也完成制定802.16e-2005這個以OFDMA傳輸技術為主的新規範。 OFDM系統和其他傳統的傳輸系統最主要的相異點就是他在同一Symbol中擁有相當多的子載波(sub-carrier)，而子載波間所遭遇的通到干擾相關性較高，所以在系統中固定的子載波上傳送已知的訊號(pilot)來估測通道對接收訊號所造成的影響，在此稱為(Channel Estimation)。在一個用戶端的接收機(downlink)會遭遇到許多不同問題，如時間和頻率的同步、都卜勒效應等等。隨著TGV高速鐵路等大眾運輸交通工具的出現，原本干擾較小的都卜勒效應(Doppler Effect)所造成的影響已經明顯地干擾到收訊的品質，這也是為何在高速行駛的交通工具上我們的無線通訊產品常常無法正常接收的重要原因。有鑒於此，我們希望能設計出一個基於IEEE 802.16e-2005提出的架構，並且能在高速環境下仍能夠保持良好通訊品質的接收機。在此我們引入多輸入多輸出的天線傳輸技術MIMO(Multiple-Input Multiple-Output)來獲得Antenna Diversity Gain並使用適當的頻率編碼和ICI消除機制來達成我們的目標。
本篇論文中提出完整的inner系統接收機架構，真對高速環境下雜訊的干擾對系統進行修更，讓系統效能在高速下仍能夠正常運作，本系統採用SFBC的架構，利用多根天線傳送相關編碼資料的方式保護原本的傳送資訊。也就是利用資料流量的減少換取資料的正確性。
在ICI干擾的部分，本論文中利用ICI消除的模組，在高速環境的情況下將ICI的干擾先估測出來然後再扣除的方式使系統的效能能夠更好，不過因為此演算法在實現上的困難度跟複雜度太過高，而且期改善能力受到限制，故最後實作的部分沒有考慮此部分的設計。
另外，在硬體設計方面，也盡可能將運算複雜度先化簡在進行設計，讓系統的實現變得更容易，最後有physical的相關實現設計，將整個系統以最真實的角度去考量實作的可行性。

In this paper, a 4x4 multiple-input multiple-outputorthogonal frequency division multiple
access (MIMO-OFDMA) downlink transceiver based on IEEE 802.16e-2005 standard is
proposed.
Under high mobility environment, wireless channel is effected by Doppler Effect critically.
A low complexity Channel-estimator is proposed in this thesis for detecting the channel
information which change rapidly in high mobility environment and a simplified pipelined
SFBC decoder is also proposed to demodulate the received signal.
Moreover, an ICI-compensation system is proposed to mitigate the Doppler Effect and
provide an extra gain of 2.5 dB for the system in certain condition. When the mobility reach
300 km/hr, the BER can still hold on about 10��3 for QPSK in the proposed system.
Physical design will focus on the operation of frequency domain in the system. Some part
of the system will be ignored to pursue a low power and low cost chip design.
The maximum operating frequency is 62.5 MHz and the area is 356 (K) in gate-count for
the proposed design. The maximum throughput of the proposed design is 51.3 Mbps for each
user in the system under 16-QAM modulation operation.

1 Introduction 1
1.1 Background of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 WiMAX Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 OFDM Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Motivation of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 System Description 5
2.1 Introduction of IEEE 802.16e Standard . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 OFDM System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Symbol Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3 Subcarrier Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 MIMO System Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Architecture Design 13
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Architecture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1 SFBC Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.2 Pilot Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3 Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.4 Inverse Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . 18
3.4 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.1 Step.1: Timing Synchronization . . . . . . . . . . . . . . . . . . . . 19
3.4.2 Step.2: Fractional CFO and Integer CFO Compensation . . . . . . . 20
3.4.3 Step.3: Data Demodulation . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 System Performance Results . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5.1 System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5.2 System Performance with Outer . . . . . . . . . . . . . . . . . . . . 31
4 Logic Design 39
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2 System Performance and Word-length Determination . . . . . . . . . . . . . 40
4.2.1 Worst case Determination . . . . . . . . . . . . . . . . . . . . . . . 40
4.2.2 Word-Length Determination . . . . . . . . . . . . . . . . . . . . . . 40
4.2.3 System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3 Hardware Architecture for Whole System . . . . . . . . . . . . . . . . . . . 42
4.3.1 Input Signal Normalization . . . . . . . . . . . . . . . . . . . . . . . 43
4.3.2 Input Block Memory Arrangement . . . . . . . . . . . . . . . . . . . 43
4.3.3 Channel Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3.4 SFBC Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.5 CSI Slope Calculation . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3.6 Channel Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3.7 Feedback Loop Design . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4 Discussion and Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5 Implementation Results 65
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2 Hardware Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.3 Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.1 APR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.2 DRC and LVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.3 Post-Layout Simulation and Chip Layout . . . . . . . . . . . . . . . 70
5.3.4 Power and Gate-Count Analysis . . . . . . . . . . . . . . . . . . . . 70
5.3.5 Chip Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6 FutureWorks and Conclusions 75
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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