臺灣博碩士論文加值系統

在本篇論文中，我們提出一新的二元符號算術編碼資料壓縮演算法，並建
立一個灰色適應性預測器做為我們演算法中機率估計模組調整機率更新步
伐之依據，以提昇適應性機率估計編碼器之壓縮率。另外又設計一使用於
Markov Process下，實現以上算術編碼器之硬體架構，此架構中將整個算
術編碼分割成二段(stage)，進行時序相鄰資料之管線式 (pipeline)平行
處理、及內部算術運算及資料存取間之平行處理架構,及線結式控制器,內
部架構之功能單元(functional unit)化設計，最後使用硬體描述語言
Verilog，配合電腦輔助設計軟體Cadence環境下，進行硬體架構之模擬與
驗證。由於內部算術運算及資料存取間之平行處理，估計約可以達到
12.5M bits / per second 之編/解碼速度。

In this paper, we propose a new adaptive arithmetic
coding algorithm for lossless data compression and
decompression . In it, a Grey theory based predictor is used
as a tuner , which dynamically determines the probability
tuning scale for next input symbol , to improve compression
efficiency. Under the order-16 Markov process , a 2-pipeline
stages parallel architecture for the algorithm has been
designed . The proposed hardware architecture exploits the
principles of pipelining and parallelism of compression
operations in the algorithm to obtain a high speed and
throughput. By Verilog simulation, it can yield a compression
and decompression rate of about 12.5 M bits/sec with a clock
rate of 25 MHz.