臺灣博碩士論文加值系統

在很多電路的應用上，必須利用鎖相迴路器提供一個緊密跟隨輸入時脈的輸出時脈信號。例如時脈訊號的產生與資料回復以及頻率合成器、調頻器、解頻器的應用上。而隨著環璄所需時脈速度的增加，鎖相迴路器的抖動效能也越來越重要。而鎖相迴路器的抖動來源主要來自其非理想效應，如電源供應器雜訊、基板雜訊、壓控振盪器雜訊跟電流泵浦所產生的電流不對稱。
而在這篇論文主要提出了預估抖動效能的方法，來預估由不同雜訊源所造成的輸出抖動。而在一開始會先利用Hspice和Spectre去預估不同雜訊源所造成的相位雜訊，之後再利用相位雜訊轉抖動公式及雜訊轉換方程式來預估鎖相迴路器的輸出抖動。
而本次的研究主要把重點放在分析鎖相迴路器本身雜訊所產生的抖動。內容可分成理論分析及鎖相迴路器各個雜訊所造成的相位雜訊:
理論分析:
在這部份為分析各個不同的雜訊所造成的相位雜訊(phase noise)，然後利用相位雜訊(phase noise)轉抖動(jitter)公式來評估鎖相迴路器的抖動量。而所考慮的雜訊包括壓控振盪器的內部雜訊，輸入時脈的相位雜訊(phase noise)，迴路濾波器上電阻的熱雜訊，以及電流泵浦和相位頻率偵測器所產生的雜訊等。最後再利用雜訊轉換方程式求得最適合的系統參數設計。
鎖相迴路器各部份相位雜訊:
在這部份所考慮的相位雜訊主要包括壓控振盪器、相位頻率偵測器及電流泵浦所造成的電流不對稱、輸入相位雜訊等部份。

In many circuits, PLL must provide an output clock to follow the input clock closely.
Examples of applications that use PLL include clock and data recovery, clock synthesis, and synchronization, frequency synthesis and PLL modulator or de-modulator application. As environment clock speed rise up, the jitter performance for PLL is more and more important. The jitter source of PLL comes from many no ideal effect of PLL, such as power supply noise, substrate noise, VCO noise, and charge pump current mismatch.
This thesis proposes the prediction method of jitter performance, for estimate the output jitter comes from each noise source. Initially, Hspice and Spectre are used to estimate the output phase noise of each noise source in coordinate with phase-noise-to-jitter transfer function and noise transfer function (NTF) to estimate the PLL output jitter.
This thesis primary considered the noise created by phase-locked loop. Include thermal analysis and the phase noise created by each block in PLL.
Thermal Analysis:
This part primarily analysis the phase noise created by each block in PLL. Then use the phase noise to jitter equation to estimate the PLL output jitter.
PLL Each Block Phase Noise:
This park primarily consider VCO phase noise、current mismatch created by PFD/CP and input clock phase noise.

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