臺灣博碩士論文加值系統

新的靜態影像壓縮標準，JPEG 2000 Part 1，在西元兩千年成為國際標準。而在西元兩千年八月標準尚在訂定的同時，我們以當時於西元兩千年三月份最新發表的JPEG 2000規格，嘗試著以硬體方式來實現此標準。
JPEG 2000標準包含了三項主要演算法，有Arithmetic Coding、Coefficient Bit Modeling及小波轉換（Discrete Wavelet Transform）。我們提出JPEG2000解壓縮硬體架購並實作成可合成的電路。
我們利用Compass Cell Library，以及台積電的0.35 μm CMOS製程來實作，最快工作頻率達40 MHz。

We proposed an architecture for the front-end part of a JPEG2000 image decoder including marker handler, arithmetic decoder and coefficient bit modeling module. The whole JPEG2000 decoder system is made up of the proposed architecture, an IDWT block and an RGB-to-BMP format converter. We have completed the RTL design and verified its functional correctness with gate-level simulation. The circuit has been synthesized targeting toward a 0.35 μm CMOS cell library. Its area is 24,700 gates and speed is 40 MHz.

ABSTRACT
CONTENTS
LIST OF FIGURES
LIST OF TABLES
1. INTRODUCTION
2. PREVIOUS WORK
3. CIRCUIT DESIGN
3-1 CHIP INTERFACE
3-2 ARCHITECTURE
3-2-1 Marker Handler
3-2-2 Arithmetic Decoder
3.2.3 Coefficient Bit Modeling
4. DESIGN FLOW AND RESULTS
4-1 DESIGN FLOW
4-2 RESULTS
5. CONCLUSIONS AND FUTURE WORK7
BIBLIOGRAPHY
APPENDIX A SOURCE CODE

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