臺灣博碩士論文加值系統

今年本實驗室提出一新型嵌入式快閃記憶元件，並且已經初步驗證元件在寫入及抹除操作下的電性變化。然而，對於該元件更深入的探討則尚未完成，也因此需要建構一個有效的模擬工具來實現這樣的工作。而由於該新型快閃記憶元件是完全相容於一般單層多晶矽閘極製程的，元件的模擬及預測工作即可藉由常用的電路模擬軟體來達成。事實上，藉由BSIM模型的幫助，一般元件特性早已是可正確模擬的，然而由於該模型缺乏閘極電流注入機制的運算，也使得相容於標準CMOS製程的新型架構在電路模擬軟體上的工作遭遇到些許的障礙。
因此，在本研究中主要有兩項工作。一是通道熱載子注入機制的等效電路元件以及該記憶體元件等效子電路模型的建立。藉由一些電阻性的耦合參數，吾人已可得到與量測資料相當吻合的模擬結果。
另一項工作則是探討各項參數對於該元件特性的影響。主要討論的設計參數有三大類，分別是元件尺寸、操作電壓的選擇，以及製程的變化。並且在本論文中，藉由物理直覺、簡單的運算以及該等效子電路模型的模擬亦已了解參數影響並且初步地驗證其趨勢。
經由本論文的討論，已初步了解元件的設計方向，並且發現該元件對於製程參數有強烈的變化。因此也引發兩個需要日後繼續研究的問題，亦即陣列架構的設計以及寫入/抹除操作方法的改進方式。

A new embedded-flash-memory cell consisting of two transistors fabricated by a standard CMOS process has been proposed by our lab. The cell is verified with good program and erase characteristics, but further investigation are not completed yet. Owing to the full compatibility with the standard CMOS process, such investigations can be fulfilled by SPICE simulations. Though accurate device characteristics is already obtained by the BSIM device model, but the lack of a sub-circuit model of the gate current injection mechanisms prohibits further studies of the cell behavior. Hence, a simulation tool compatible with SPICE is built up for cell structure optimization.
There are two major aims in this study. One is the built-up of the circuit element of hot-carrier injection and a sub-circuit model to simulate the proposed cell. Fairly good agreements between simulation results and the measurement data are obtained with our sub-circuit model.
The second aim of this study is to investigate the effect of various cell parameters on the cell behavior. Three kinds of design parameters — cell dimensions, operating voltages, and process variations — are discussed in this work. The influences of design parameters are verified with physical intuitions, hand calculation and simulation results.
Through such discussions, the design direction of the novel cell is revealed. Those conclusions therefore can help further improvement of the array structure and new program / erase schemes to obtain better cell performance.

Abstract I
Acknowledgement III
List of Contents IV
List of Figures VI
List of Tables VIII
Chapter 1 Introduction 1
Chapter 2 Review 3
2-1 Introduction 3
2-2 Hot Carrier Model 3
2-2-1 Lucky Electron Model 3
2-2-2 Drift-Diffusion Model 5
2-2-3 Summary 6
2-3 Flash cells with single polycrystalline silicon process 6
2-3-1 SIPPOS (single poly pure CMOS) 6
2-3-2 ie-Flash 7
2-3-3 Summary 7
Chapter 3 Cell Structure and Operation Basics 13
3-1 Introduction 13
3-2 Cell Structure 13
3-3 Cell Operation Principles 13
Chapter 4 Measurement Setup and Sub-Circuit Modeling 20
4-1 Introduction 20
4-2 Compact Model for Hot Carrier Injection 20
4-3 Measurement Setup 23
4-4 Extraction Procedure 23
4-5 Simulation Procedure 24
4-5-1 Equivalent Circuit 24
4-5-2 Simulation Procedure 25
4-6 Verification of Compact Model 26
4-6-1 Parameter Extraction for the Compact Model 26
4-6-2 Model Prediction on Cell Behavior 26
Chapter 5 Cell Design and Optimization 38
5-1 Introduction 38
5-2 Impacts of Variables 38
5-2-1 Cell Dimension 38
5-2-2 Operation Voltage 43
5-2-3 Process Variation 44
5-3 Optimization of New Memory Cell 45
5-4 Short Discussion on the Scaling Trend 46
5-5 Summary 47
Chapter 6 Conclusion 60
Appendix I List of Variables 61
Appendix II Simple Calculation on Cell Operation 62
Appendix III References 70
Appendix IV Simulation Code 72

[1] “An Experimental 5-V-Only 256-kbit CMOS EEPROM with a High -Performance Single-Polysilicon Cell,” Jun-ichi Miyamoto et al., p. 852 — 860, Vol. SC-21, IEEE Solid -State Circuits, 1986
[2] “Advanced Electrical-Level Modeling of EEPROM Cells,” Massimo Lanzoni et al., p. 951 — 957, Vol. 40, IEEE TED
[3] “Macromodel Development for a FLOTOX EEPROM,” Kenneth V. Noren et al., p. 224 — 229, Vol. 45, IEEE TED, 1998
[4] “A SPICE-compatible Flash EEPROM Model Feasible for Transient and Program / Erase Cycling Endurance Simulation,” C. —M. Yih et al., IEDM, 1999
[5] “Lucky-Electron Model of Channel Hot-Electron Injection in MOSFET’s,” Simon Tam et al., ED-31, IEEE TED, 1984
[6] p. 170 — 174, Advanced Theory of Semiconductor Devices, Karl Hess, 2000
[7] “Recent Advances in Transport Modeling for Miniaturized CMOS Devices,” T. Grasser et al., Fourth IEEE International Caracas Conference on Devices, Circuits and Systems, 2002
[8] “Consistent Gate and Substrate Current Modeling Based on Energy Transport and the Lucky Electron Concept,” Bernd Meinerzhagen, IEDM, 1988
[9] “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,” Katsuhiko Ohsaki et al., p.311- 316, Vol. 29, IEEE J. of Solid-State Circuits, 1994
[10] “1.25 Volt, Low Cost, Embedded Flash Memory for Low Density Applications,” Richard J. McPartland et al., VLSI Symposium, 2000
[11] To be published
[12] “Emission probability of Hot electrons from Silicon into Silicon dioxide,” T. H. Ning et al., p. 286 — 293, Vol. 48, J. of applied Physics, 1977
[13] “Enhanced Reliability in Si MOSFETs with Channel Lengths under 0.2 Micron,” Lindor Henrickson et al., p. 1275 — 1278, Vol. 33, Solid-State Electronics, 1990
[14] “Dependence of Channel Electric Field on Device Scaling,” T. Y. Chan et al., p. 551 — 553, Vol. EDL—6, IEEE EDL, 1985
[15] “Hot-Electron Currents in Deep-Submicrometer MOSFETs,” J. Chung et al., p. 200 — 203, IEDM, 1988
[16] “Temperature Dependance of the Channel Hot-Carrier Degradation of n-Channel MOSFET’s,” Paul Heremans et al., p. 980 — 993, Vol. ED-37, IEEE TED, 1990
[17] P47, Physics of Semiconductor Devices, 2nd edition, S. M. Sze, 1981
[18] Appendix H, Physics of Semiconductor Devices, 2nd edition, S. M. Sze, 1981
[19] “Hot-Electron and Hole-Emission Effects in Short n-Channel MOSFET’s,” Karl R. Hofmann et al., p. 691 — 699, Vol. ED—32, IEEE TED, 1985
[20] “A simple Method to Characterize Substrate Current in MOSFET’s,” T. Y. Chan et al., p. 505 — 507, Vol. EDL—5, IEEE EDL, 1984
[21] “A Modified Lucky Electron Model for Impact Ionization Rate in NMOSFET’s at 77 K,” C. H. Ling et al., p. 263 — 266, Vol. 46, IEEE TED, 1999
[22] p. 3-15, BSIM 3v3 manual, 1996
[23] p. 15-74, Star-HSPICE Manual, 1998
[24] “Source-and-Drain Series Resistance of LDD MOSFET’s,” B. J. SHEU et al., p. 366 — 368, Vol. EDL—5, IEEE EDL, 1984
[25] “A physical-Based Semi-Empirical Series Resistance Model for Deep-Submicron MOSFET I-V Modeling, ” K. Y. Lim et al, p. 1300 — 1302, Vol.47, IEEE TED, 2000