臺灣博碩士論文加值系統

隨著科技的進化與演變，現代人們的生活與無線科技緊密地結合在一起。無線射頻辨識系統(Ratio Frequency Identification, RFID)能在數公分至數公尺之距離做非接觸式辨識，為無處不在計算領域中最受矚目的技術之一。於無所不在計算(Ubiquitous Computing)所提出的概念中，我們可以在任何時間，任何地點經由規劃的系統設備來取得計算資源，並配合精確定位及智慧物件的使用，使得無所不 在的系統更具有情境感知(context awareness)的特性。被動式超寬頻無線射頻辨識技術廣泛被採用在位置感知系統運用上。此乃因被動式超寬頻RFID標籤具有低成本、小面積、無電池附著之優點，且相較於高頻標籤，其亦擁有較佳的反應速率及較長的讀取範圍。本論文，提出將超寬頻無線射頻辨識系統技術運用於建構定位感知系統。UHF RFID系統上之天線，為傳送功率及訊號之主要元件。因此，在UHF RFID系統上，讀取天線便為關鍵技術之一。本論文設計及模擬一圓極化貼片天線，此天線可運用於位置感知系統以達到較大之效能。相較於以往根據每一個單獨的參考標籤計算出追蹤標籤位置的演算法，本論文提出群聚定位演算法來改善追蹤精 確度。在群聚定位演算法的基礎下，可讓系統在3D定位之估算能夠有更合理的精確度。此外，本論文亦提出利用CORDIC演算法計算餘弦定理，並將其以FPGA硬體實現，藉以研發提高位置感知系統之定位效能。

Radio Frequency Identification (RFID) has been considered as an attractive method for the ubiquitous computing. One area of ubiquitous computing is composed by the location-aware systems, systems where applications are designed to estimate the coordinates of tracking objects in qualified vicinity or in correlation to reference locations. The passive UHF RFID system is an attractive solution for location awareness applications. Passive UHF RFID tags have gained significant popularity due to their low cost, small footprint, ability to function without batteries, faster response rates and longer read ranges as compared to common HF RFID tags.
In this thesis, a location-aware systems based on passive UHF RFID technology is proposed. In UHF RFID system, the role of antennas is very important for transfer power and signal. Therefore, reader antenna is a key important component of RFID system. The design and simulation of a patch antenna with circular polarization is presented. A circularly-polarized antenna can help maximize performance of the location awareness system. In contrast to compute the position of the tracking tag based on each individual reference tag, a cluster localization algorithm is introduced to improve the tracking accuracy. Based on the proposed cluster localization algorithm, the performance of the system was within the reasonable accuracy for 3D location estimation. In addition, the FPGA implementation of law of cosines based on CORDIC algorithm is proposed in order to study the feasibility of enhancing the performance of a location awareness system.

LIST OF TABLES iii
LIST OF FIGURES iv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overview of Position Techniques 1
1.3 Thesis Outline 3
Chapter 2 RFID Technology 4
2.1 Introduction to RFID 4
2.2 RFID Tags 4
2.3 RFID Readers 6
2.4 RFID Frequency Bands 6
2.5 Near-Field and Far-Field Propagation 7
2.6 A Review of RFID Localization Algorithms 9
2.6.1 Triangulation Algorithm 10
2.6.2 Scene Analysis 10
2.6.3 Proximity 10
Chapter 3 RFID Antenna Design 11
3.1 Introduction 11
3.2 Reader Antenna Design 12
3.2.1 Design Principles 12
3.2.2 Antenna Modeling 13
3.2.3 Antenna Configurations 15
3.3 Experimental Results 17
3.4 Discussion 20
Chapter 4 RFID Location Awareness System 21
4.1 Introduction 21
4.2 Localization Algorithm 22
4.2.1 Matching Phase 23
4.2.2 Estimation Phase 24
4.2.3 Optimal Custer Formation Phase 25
4.3 System Implementation 28
4.4 Experimental Work 29
4.5 Discussion 39
Chapter 5 CORDIC Technique For RFID Localization 40
5.1 Basic CORDIC Algorithm 40
5.2 Triangulation Location Estimation Method 43
5.3 Implementation 45
5.3.1 IEEE Floating Point 45
5.3.2 Law of Cosines Implementation Based on CORDIC Algorithm 47
5.4 Summary 56
Chapter 6 Conclusion 57
6.1 Conclusion 57
6.2 Future Work 58
References 59
Table I. RFID tags: Active vs. passive 5
Table II. RFID frequency bands and corresponding application areas 7
Table III. Reference tags data list for tracking tag T1 31
Table IV. Reference tags data list for tracking tag T2 32
Table V. Comparison of tracking results for tags T1 and T2 33
Table VI. Read counter strength of tracking tag T1 36
Table VII. Location estimation of tracking tag T1 36
Table VIII. Iterated results for the estimated location of the tracking tag 36
Table IX. Iterated results for the estimated location of the tracking tag 37
Table X. Final iteration results for the location estimation of tracking tag T1 37
Table XI. Database of statistical analysis on some results 38
Table XII. IEEE 754 45
Fig. 1.1 Current positioning systems according to their accuracy and coverage area 2
Fig. 2.1 Basic component of a RFID system 4
Fig. 2.2 RFID tags architecture 5
Fig. 2.3 Antenna near-field & far-field transition regions 8
Fig. 3.1 Patch antenna model 13
Fig. 3.2 Basic rectangular patch antenna 14
Fig. 3.3 Show the proposed geometry of truncated rectangular patch antenna. (a) schematic top view, (b) schematic side view, and (c) photo of proposed antenna 16
Fig. 3.4 Simulated return losses for patch antenna with and without L-shaped vertical ground feed line 17
Fig. 3.5 Measured and simulated return loss for the proposed patch antenna 18
Fig. 3.6 Measured 3D gain radiation patterns of the proposed antenna at 922 MHz. The pattern data as a function of theta (θ), phi (Φ) and total gain radiation pattern 19
Fig. 3.7 Measured peak antenna gain versus frequency for the proposed antenna 19
Fig. 3.8 Measured axial ratio of the proposed CP antenna at Taiwan/US bands 20
Fig. 4.1 The RFID location awareness system architecture 22
Fig. 4.2 RFID passive tags localization model 23
Fig. 4.3 The location estimation algorithm of finding the tracking tag 27
Fig. 4.4 The main modules in location awareness system 28
Fig. 4.5 RFID data acquisition system 29
Fig. 4.6 The measured counter intensity results for T1 in z (1.3) Plane 34
Fig. 4.7 The measured counter intensity results for T2 in z (1.3) Plane 34
Fig. 4.8 The measured counter intensity results for T1 in z (1.6) Plane 35
Fig. 4.9 The measured counter intensity results for T2 in z (1.6) Plane 35
Fig. 4.10 Standard Deviation of the analyzed data 38
Fig. 5.1 The reader location estimated by the angulation technique 44
Fig. 5.2 Simulation results of half precision floating-point format 46
Fig. 5.3 Simulation results of single precision floating-point format 46
Fig. 5.4 Simulation results of double precision floating-point format 47
Fig. 5.5 Law of cosines implementation based on CORDIC algorithm 47
Fig. 5.6 Architecture of the floating point adder 48
Fig. 5.7 Block diagram of the CORDIC-based arithmetic unit 48
Fig. 5.8 The results of the sine functional simulation 49
Fig. 5.9 CORDIC calculation results 50
Fig. 5.10 Verification waveform for X signal 50
Fig. 5.11 Verification waveform for Y signal 51
Fig. 5.12 Verification waveform for Y signal 51
Fig. 5.13 ASM chart for calculating the law of cosine based on CORDIC algorithm 52
Fig. 5.14 Verilog waveform verification of the law of cosine 53
Fig. 5.15 The measurement results of the logic analyzer for FPGA implementation 53
Fig. 5.16 ASM chart for calculating the law of cosine based on CORDIC algorithm 54
Fig. 5.17 Verilog waveform verification of the law of cosine 54
Fig. 5.18 Hardware verification results from the FPGA are displayed using HP16702A Logic Analysis System 55

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