臺灣博碩士論文加值系統

鎖相迴路電路乃是積體電路發展中不可缺少的電路架構，其功能為頻率合成，去除時脈偏斜，減少時脈抖動以及時脈/資料回復，所以在積體電路的應用中常常可以看到鎖相迴路電路。而在設計電路的同時，也需要有測試的概念，以降低晶片完成後的測試成本。本論文就是針對鎖相迴路的電路設計與測試考量做研究報告。
在本論文中我們設計了一個震盪頻率在1~1.5GHz的鎖相迴路，其輸入頻率約在30~50MHz，電路包括相位偵測器、電荷幫浦、迴路濾波器、壓控震盪器與除頻器等基本單元，並利用tsmc 0.35um 1P4M 3V的製程技術實現。在鎖相迴路的測試中，是依據[6]中關於晶片中鎖相迴路時脈抖動量測的架構提出改良，由於[6]架構中的D型正反器會有設定時間與保持時間的問題，所以將D型正反器換成時脈抖動偵測器，並且將固定延遲去除，來量測晶片中的時脈抖動。測試電路經由相位等分器可達到25ps的解析度，且可藉由觀察數位電路輸出得知時脈抖動的統計值。鎖相迴路與測試電路皆採取使用全客戶委託式設計流程實現。

第一章 簡介….…………………………………………………………....1
1.1 研究動機…………………………………….………………………. …1
1.2 論文架構組織.……………………………………………… …….……2
第二章 研究背景與先前相關研究成果...………………………………..4
2.1 研究背景….……………………………………………………...…….4
2.1.1 鎖相迴路電路基本架構及線性小信號模型……………………….…4
2.1.2 鎖相迴路電路中的重要參數….……………………….………….…8
2.1.3 鎖相迴路的優點…………………………………….………… …….9
2.2 先前相關研究成果……….……….……………………....…………11
2.2.1 鎖相迴路電路……………….………………….……………… ….12
A. 頻率合成器…….……….………………….…………………………..12
B. 時脈/資料回復電路…….…...……………….……………………….13
C. 全數位鎖相迴路……….…………………….………………… ………14
D. 延遲鎖定迴路……….…………………….………………………… …16
2.2.2 鎖相迴路電路測試…………………………………………….….…16
A. 易測試設計與內建式自我測試….………………………………………16
B. 時脈抖動量測……………….……………………………………………19
第三章 1.2GHz鎖相迴路頻率合成器……………………………….………22
3.1 頻率合成器電路架構…….…………………………………………….22
3.2 壓控震盪器………………………………………………………………23
3.2.1 簡介……………………………………………………………… …23
3.2.2 電路特性與特性………………………………………………… …25
A. 電路特性……………………………………………………………… …25
B. 電路描述……………………………………………………………… …26
3.3 除頻器………… …………………………………………………… …27
3.4 相位偵測器……………………………………………………….… …29
3.5 電荷幫浦………………………………………………………….… …31
3.6 迴路濾波器……………………………………………………….… …32
3.7 電路模擬結果…………………………………………………….…… 34
第四章 晶片中時脈抖動量測……………………………………….………38
4.1 鎖相迴路內建自我測試簡介……………………………………..……38
4.2 時脈抖動偵測器…………………………………………………..……42
4.3 相位攪拌器………………………………………………………..……46
4.4 時脈抖動測試架構………………………………………………..……48
第五章 結論與未來工作……………………………………………..……53
參考文獻 ………………………………………………………………….…55

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