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When conventional digital transmission systems are unable to
support a wide variety of services, the Broadband Integrated
Service Digital Networks (B-ISDN) are proposed to integrate
various services. A new payload multiplexing technique, called
asynchronous transfer mode (ATM), has been proposed as the
transfer mode for implementing the B-ISDN. Many people are
engageed in the research of the ATM product. The purpose of the
thesis is to design a VLSI ASIC ( Application Specific
Integrated Circuit ) which is used in the user network
interface. The interface consists of continuous stream of
cells, with no multiplex frame structure imposed at the
interface. The chip performs some B-ISDN physical layer
functions at the user network interface, such as cell
delineation, cell rate decoupling, HEC sequence generation and
cell header verification. It transmits and receives the serial
signals with the speed of 155Mbps. In addition to functions
described previously, the IC scrambles the ATM cells in order
to reduce a long string of 0's or 1's and to improve the
transmission performance. The circuit is implemented in CMOS
0.8um technology with approximately 1,200 gates counts and with
a die area 3 * 2.7 mm^2. The simulation speed is about 75Mhz.
The chip is packaged in DIP (Dual-in-line Package) with 48
pins. The future work is to reduce the delay of the critical
path in the cell delineation module. It will improve the chip
performance.
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