Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Related Works 3
1.3 Objectives of the Thesis 4
1.4 Organization of the Thesis 5
Chapter 2 Auditory Source Localization Basics 6
2.1 Principle of Hyperbolic Auditory Localization 7
2.2 Time Difference of Arrival (TDOA) 9
2.3 Average Magnitude Difference Function (AMDF) 11
2.4 Auditory Source Localization System Overview 14
Chapter 3 Chip Design and Implementation 15
3.1 System Flow Chat and System Architecture 15
3.2 ADC and I2S 17
3.3 Voiced Activity Detection (VAD) 19
3.4 SRAM and Circular Buffer Mechanism 21
3.4.1 SRAM 21
3.4.2 Circular Buffer 23
3.5 Subtraction Absolute Accumulation (SAA) and Folding 24
3.6 Circuit Diagram of Control Unit and Data Capture 27
3.7 ASIC Cell-Based Design Flow 28
3.8 Design for Testability 30
3.8.1 Scan Chain 30
3.8.2 Memory BIST 31
Chapter 4 Simulation and Verification Results 34
4.1 FPGA Simulation and Results 34
4.1.1 FPGA Experimental Setup 34
4.1.2 Hardware Development Environment 35
4.2 Chip Simulated Results 37
4.2.1 Pre-Simulated Results 38
4.2.2 Gate Level Post-Simulated Results 39
4.2.3 Transistor Level Post-Simulation Results (PVS) 40
4.3 Chip Layout and Timing Verification 43
4.3.1 Layout 43
4.3.2 Layout Verification 44
4.3.3 I/O Pin and Specification Table 45
Chapter 5 Chip Measurement 47
5.1 CIC Agilent 93K SoC Test System 47
5.1.1 ASCII Interface 48
5.1.2 Design a Device Under Test (DUT) Board 51
5.1.3 Testing Timing Diagram 52
5.2 Test Board and Prototype Chip 53
Chapter 6 Conclusion and Future Work 54
6.1 Performance Compared with Related Work 54
6.2 Conclusion 55
References 56
Appendix 58
A. Tapeout Review Form (for Cell-Based IC) 58
B. Layout and Pin Mapping 62
C. Bonding and Pin Mapping 63
D. Chip and Pin Mapping 64
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