臺灣博碩士論文加值系統

數位訊號處理需要高精確度提升訊號處理的品質及足夠的動態範圍避免發生溢位，浮點數算數為同時滿足此兩項需求最直接的解決方案，其將數值資訊以尾數及指數分別儲存，並在運算過程中動態地將每筆數值正規化至純小數，因此它能夠在極大的動態範圍下，以指數刻度提供固定位數的精確度。但浮點數算數需要極複雜的硬體動態處理數值中的指數及尾數，其成本過高且浪費能源，並不適合大多數的嵌入式系統應用；目前常見的替代方案是採取整數算數，但其依賴程式設計師手動分析運算過程，需要頻繁的數值調整及繁瑣的演算法模擬以避免運算發生溢位。本論文提出一適用於嵌入式訊號處理之輕量型算數 – 靜態浮點算數，其以軟體方式靜態分析數值之範圍，並將資料以類似浮點數之尾數的正規化純小數表示，而其正規化之係數(類似浮點數之指數)則僅紀錄於分析軟體中，不額外佔資料空間；接著以軟體工具依據此正規化係數，靜態安插對齊小數點或正規化結果等的移位動作。以IEEE 754單精準度的浮點數算術為基準，模擬結果顯示我們所提的十六位元靜態浮點算術可達到40.1802dB之訊噪比。另外，我們亦將此靜態浮點算數成功地應用在精簡化的數位訊號處理器設計之中。此核心中的運算引擎是以串流介面單元為基礎，針對常見的訊號處理演算法所開發。除上述輕量型算術之靜態分析軟體，我們也借用高階合成之技術完成此處理器核心之軟體發展工具的研發，能將以浮點算數描述之高階語言，自動轉換成產生支援靜態浮點算數之微程式碼。相對於市面常見之雙核處理器中的數位訊號處理器核心，此精簡化的核心可以不到三分之一的時脈數完成訊號的處理。最後，此內建靜態浮點算數之數位訊號處理器核心已完成以UMC 0.18μm CMOS製程、標準單元設計之晶片實作並經由CIC下線，其操作頻率為314 MHz，平均消耗52mW功率，而其核心面積為1.7mm×1.7mm。

Digital signal processing demands higher precision and enough dynamic range to improve the quality and prevent the overflow respectively. The most straightforward way to satisfy both is to use the floating-point arithmetic, where the data samples are individually represented in the exponent and the mantissa parts. Data are normalized for every operation dynamically, and therefore it provides very wide dynamic range and fixed bit-width precision in the exponential scales. However, the floating-point arithmetic needs complicated hardware to manipulate the exponent and mantissa parts dynamically, and it is not suitable for most embedded applications with cost and power constraints. Integer arithmetic is a common alternative with much simpler hardware, which relies on the programmers to extensively simulate the algorithms and insert scaling operations manually to prevent overflow. This thesis presents a lightweight arithmetic for embedded signal processing – the static floating-point (SFP) arithmetic. Variables are analyzed statically with software to estimate their dynamic ranges and they are represented in the normalized fractional accordingly, which is similar to the mantissa of the floating-point numbers. The normalization factors (similar to the exponent) are recorded and tracked implicitly in the analysis software only. Then, the automation software inserts the shift operations depending on the normalization factors for radix alignment and normalization. The simulation results show the 16-bit SFP arithmetic has 40.1802dB signal to round-off noise error over the IEEE 754 single-precision floating-point arithmetic. Finally, we have successfully integrated the proposed SFP arithmetic into a compact DSP core, which is designed for common DSP kernels based on the stream interface unit. We have also developed a complete development software to convert the floating-point algorithmic descriptions into the microcodes for the proposed DSP core, which achieves about 3X performance (estimated in cycles) with similar computing resources to those of the conventional DSP for the multi-core SoC architecture. Finally, we have implemented the DSP core in the UMC 0.18μm 1P6M CMOS technology with cell-based design flow. The operating frequency is 314 MHz with 52mW power consumption and the core size is 1.7mm×1.7mm.

ABSTRACT (CHINESE) i
ABSTRACT (ENGLISH) iii
ACKNOWLEDGEMENT v
CONTENTS vii
LIST OF TABLES ix
LIST OF FIGURES xi
1 INTRODUCTION 1
1.1 DSP ARITHMETIC 2
1.2 EMBEDDED COMPUTATIONS 4
1.3 THESIS ORGANIZATION 7
2 BACKGROUND 9
2.1 DATAFLOW COMPUTATIONS 9
2.2 HIGH-LEVEL SYNTHESIS 12
3 LIGHTWEIGHT DSP ARITHMETIC 19
3.1 DSP ARITHMETIC 19
3.1.1 Floating-point (FP) arithmetic 20
3.1.2 Integer arithmetic 22
3.2 PROPOSED STATIC FLOATING-POINT (SFP) ARITHMETIC 23
3.2.1 Static range analysis 24
3.2.2 FP to SFP conversion 26
3.3 IMPROVEMENTS 26
3.3.1 Affine analysis 27
3.3.2 Saturated arithmetic 28
3.3.3 Block floating-point 32
3.4 SUMMARY 33
4 COMPACT DSP CORE & ITS SOFTWARE GENERATION 35
4.1 DSP ENGINE 36
4.1.1 Stream interface unit (SIU) 36
4.1.2 Static floating-point unit 41
4.2 PROPOSED DSP CORE 43
4.2.1 Instruction and data memory 45
4.2.2 Control mechanism and address generation 47
4.2.3 System interface 50
4.3 SOFTWARE DEVELOPMENT 51
4.3.1 SDFG simulator 52
4.3.2 Static floating-point converter 53
4.3.3 ILP-based scheduler 54
4.3.4 Microcode generator 59
4.4 SUMMARY 59
5 SIMULATION & IMPLEMENTATION RESULTS 61
5.1 ROUND-OFF ERROR ANALYSIS 61
5.2 PERFORMANCE EVALUATION 66
5.3 IMPLEMENTATION RESULTS 69
5.3.1 FPGA prototyping 71
5.3.2 Silicon implementation 74
6 CONCLUSION & FUTURE WORK 77
REFERENCE 79
APPENDIX TOOL CHAIN 81

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