|
[1].Y. Matsueda, T. Ozawa, M. Kimura, T. Itoh, K. Kitwada, T. Nakazawa, and H. Ohsima, “A 6-bit-color VGA low-temperature poly-Si TFT-LCD with integrated digital data drivers,” in SID Tech. Dig., pp. 879-882, 1998. [2].H. Oshima and S. Morozumi, “Future trends for TFT integrated circuits on glass substrates,” in IEDM Tech. Dig., pp.157, 1989. [3].工業材料-光電特刊, Vol. 199, 2003年7月. [4].M. Stewart, R. S. Howell, L. Pires, and M. K. Hatalis, “ Polysilicon TFT technology for active matrix OLED displays,” IEEE Trans. Electron Devices, Vol. 48, pp. 845-851, 2001. [5].Mark Stewart, Robert S. Howell, Leo Pires, Miltiadis K. Hatalis, Webster Howard, and Olivier Prache, “Polysilicon VGA active matrix OLED displays – technology and performance,” in IEDM Tech. Dig., pp. 871-874, 1998. [6].H. Kuriyama et al., “An asymmetric memory cell using a C-TFT for ULSI SRAM,” Symp. On VLSI Tech., pp.38, 1992. [7].T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanala, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, and T. Nagano, “Advanced TFT SRAM cell technology using a phase-shift lithography,” IEEE Trans. Electron Devices, Vol. 42, pp.1305-1313, 1995. [8].A.Sato, Y. Momiyama, Y. Nara, T. Sugii, Y. Arimoto, T. Ito, “A 0.5-μm EEPROM cell using poly-Si TFT technology,” IEEE Trans. Electron Devices, Vol.40, pp. 2126, 1993. [9].N. D.Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French , “The fabrication and characterization of EEPROM arrays on glass using a low-temperature poly-Si TFT process,” IEEE Trans. Electron Devices, Vol. 43, pp. 1930-1936, 1996. [10].T. Kaneko, Y. Hosokawa, M. Tadauchi, Y. Kita, and H. Andoh, “400 dpi Integrated Contact Type Linear Image Sensors with Poly-Si TFT’s Analog Readout Circuits and Dynamic Shift Registers,” IEEE Trans. Electron Devices, Vol.38, No.5, pp. 1086-1039, 1991. [11].Y. Hayashi, H. Hayashi, M. Negishi and T. Matsushita, “ A Thermal Printer Head with CMOS Thin-Film Transistors and Heating Elements Integrated on a Chip,” IEEE Solid-State Circuits Conference, pp.266, 1998. [12].N. Yamauchi, Y. Inaba and M.Okamura, “An integrated photodetector-amplifier using a-Si p-i-n photodiodes and poly-Si thin-film transistors,” IEEE Photonics Tech. Lett., Vol. 5, No. 3, 1993. [13].M. G. Clark, “Current status and future prospects of poly-Si devices,” IEE Proc. Circuits Device Syst., Vol. 141, No. 1, 1994. [14].Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat, “3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration,” Proceedings of the IEEE, Vol. 89, pp. 602-633, 2001. [15].Y. Akasaka, “ Three-Dimensional IC trends,” Proceedings of the IEEE, Vol.74, No. 12, pp. 1703-1714, 1986. [16].I-W. Wu, “Cell design considerations for high-aperture-ratio direct-view and projection polysilicon TFT-LCDs,” in SID Tech. Dig., pp. 19-22, 1995. [17].W. G. Hawkins, “Polycrystalline-silicon device technology for large-area electronics,” IEEE Trans. Electron Devices, Vol. 33, pp. 477-481, 1986. [18].M. Takabatake, J. Ohwada, Y. A. Ono, K. Ono, A. Mimura, and N. Konishi, “CMOS circuits for peripheral circuit integrated poly-Si TFT LCD fabricated at low temperature below 600 °C,” IEEE Trans. Electron Devices, Vol. 38, pp. 1303-1309, 1991. [19].John Y. W. Seto, “ The electrical properties of polycrystalline silicon film,” J. Appl. Phy., Vol.46, No. 12, pp. 5247-5254, 1975. [20].J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “ Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phy., Vol. 53, No. 2, pp. 1193-1202, 1982. [21].S. D. Brotherton, J.R. Ayres, and N. D. Young, “ Characterisation of Low Temperature Poly-Si Thin Film Transistors,” Solid-State Electronics, Vol. 34, No. 7, pp. 671-679, 1991. [22].I.-Wei Wu, Alan G. Lewis, Tiao-Yuan Huang, Warren B. Jackson, and Anne Chiang, “Mechanism and device-to-device variation of leakage current in polysilicon thin film transistors,” in IEDM Tech. Dig., pp. 867-870, 1990. [23].K. R. Olasupo, and M. K. Hatalis, “Leakage current mechanism in sub- micron polysilicon thin- film transistors,” IEEE Trans. Electron Devices, Vol. 43, pp. 1218-1223, 1996. [24].M. Lack, I-W. Wu, T. J. King, and A. G. Lewis, “Analysis of leakage currents in poly-silicon thin film transistors,” in IEDM Tech. Dig., pp. 385-388, 1993. [25].Jerry G. Fossum, Adelmo Ortiz-conde, Hisashi Shichijo, and Sanjay K. Banerjee, “Anomalous Leakage Current in LPCVD Polysilicon MOSFET’s,” IEEE Trans. Electron Devices, Vol. 32, No. 9, pp. 1878-1884, 1985. [26].M. Yazaki, S. Takenaka, and H. Ohshima, “Conduction Mechanism of Leakage Current Observed in Metal-Oxide-Semiconductor Transistors and Poly-Si Thin Film Transistors,” Jpn. J. Appl. Phys., Vol. 31, pp. 206-209, 1992. [27].Bohuslav Rezek, Christoph E. Nebel, and Martin Stutzmann, “Polycrystalline silicon thin films produced by interference laser crystallization of amorphous silicon,” Jpn. J. Appl. Phys., Part 2, Vol. 38, pp. L1083-L1084, 1999. [28].P. M. Smith, P. G. Carey, and T. W. Sigmon, “Excimer laser crystallization and doping of silicon films on plastic substrates,” Appl. Phys. Lett., Vol. 70, pp. 342-344, 1997. [29].James S. Im, H. J. Kim, and Michael O. Thompson, “Phase transformation mechanisms involved on excimer laser crystallization of amorphous silicon films,” Appl. Phys. Lett., Vol. 63, pp. 1969-1971, 1993. [30].Yunosuke Kawazu, Hiroshi Kudo, Seinosuke Onari, and Toshihiro Arai, “Low-temperature crystallization of hydrogenated amorphous silicon induced by nickel silicide formation,” Jpn. J. Appl. Phys. Part1, Vol. 29, pp. 2698-2704, 1990. [31].K. Tanaka, H. Arai, and S. Kohda, “Characteristics of offset-structure polycrystalline silicon thin- film transistors,” IEEE Electron Device Lett., Vol. 9, pp. 23-25, 1988. [32].Byung-Hyuk Min and Jerzy Kanicki, “Electrical characteristics of new LDD poly-Si TFT structure tolerant to process misalignment,” IEEE Electron Device Lett., Vol. 20, pp. 335-337, 1999. [33].Yasuyoshi Mishima and Yoshiki Ebiko, “Improved lifetime of poly-Si TFTs with a self-aligned gate-overlapped LDD structure,” IEEE Trans. Electron Devices, Vol. 49, pp. 981-985, 2002. [34].M. Hatano, H. Akimoto, and T. Sakai, “A novel self-aligned gate-overlapped LDD poly-Si TFT with high reliability and performance,” in IEDM Tech. Dig., 1997, pp. 523-526. [35].Kwon-Young Choi, Jong-Wook Lee, and Min-Koo Han, “Gate-overlapped lightly doped drain poly-Si thin- film transistors for large area-AMLCD,” IEEE Trans. Electron Devices, Vol. 45, pp. 1272-1279, 1998. [36].Ted Kamins, Polycrystalline silicon for integrated circuits and displays, second edition. [37].M. Hack, and A. G. Lewis, “Avalanche-induced effects in polysilicon thin-film transistors,” IEEE Electron Device Lett., Vol. 12, pp. 203-205, 1991. [38].M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I. Policicchio, “Floating body effects in polysilicon thin- film transistors,” IEEE Trans. Electron Devices, Vol. 44, pp. 2234-2241, 1997. [39].M. Koyanagy, H. Kaneko, and S. Shimizu, “ Optimum design of n+-n– double-diffused drain MOSFET to reduce hot-carrier emission,” IEEE Trans. Electron Devices, Vol. 32, pp. 562, 1985. [40].F.-C Hsu, and H. R. Grinolds, “Structure-enhanced MOSFET degradation due to hot-electron injection,” IEEE Electron Device Lett., Vol. 5, No. 3, pp. 71-74, 1984. [41].J. Hui, F.-C Hsu, and J. Moll, “ A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices,” IEEE Electron Device Lett., Vol. 6, pp. 135, 1985. [42].Tiao-yuan Huang, William W. Yao, Russel A. Martin, Alan G. Lewis, Mitsumasa Koyanai, and John Y. Chen, “ A novel submicron LDD transistor with inverse-T gate structure,” in IEDM Tech. Dig., pp. 742-745, 1986. [43].T. Hori, and K. Kurimoto, “A new MOSFET with large-tilt-angle implanted drain (LATID) structure,” IEEE Electron Device Lett., Vol.9, No.6, pp.300-302, 1988. [44].T. Hori, J. Hirase, Y. Odake, and T. Yasui, “Deep-submicrometer large-angle-tilt implanted drain (LATID) technology,” IEEE Trans. Electron Devices, vol. 39, No. 10, pp. 2312-2324, 1992. [45].T. Hori, “0.25μm LATID (LArge-Tilt-angle Implanted Drain) technology for 3.3-V operation,” in IEDM Tech. Dig., pp. 777-780, 1989. [46].J. Hirase, T. Hori, and Y. Odake, “LATID (Large-Angle-Tilt Implanted Drain) FETs with buried n– profile for deep-submicron ULSIs,” IEICE Trans. Electron., Vol. 77-C, No. 3, pp. 350-354, 1994.
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