|
[1.1] Kim, “Future Memory Technology: Trends and Challenges”, Plenary paper, ISQED, 2006 [1.2] D. K. and S. M. Sze , “A floating gate and its application to memory devices”, Bell Syst. Tech, 46, 1288, 1967 [1.3] P. Pavan, R. Bez, P. Olivo and E. Zanoni, “Flash Memory Cells—An Overview,” Proc. IEEE, 85, 1248, 1997 [1.4] “International Technology Roadmap for Semiconductors, 2007 update [1.5] C.Y. Lu and C.C. Yeh, “Advanced Non-Volatile Memory Devices with Nano -Technology”, invited talk for 15th International Conference on Ion Implantation Technology, 2004 [1.6] S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, Appl. Phys. Lett., 68, 1377 (1996) [1.7] J. D. Blauwe , ”Flash Nonvolatile Memory Devices,” IEEE Trans. Nanotechnol., 1, 72 (2002) [1.8] C. H. Tu, T. C. Chang, P. T. Liu, H. C. Liu, S. M. Sze, and C. Y. Chang, Improved memory window for Ge flashs embedded in SiON layer,” Appl. Phys. Lett., 89, 162105 (2006) [1.9] Greg Atwood, ”Future Directions and Challenges for ETox Flash Memory Scaling,” IEEE Trans. on Device and Materials Reliability, Vol. 4, No. 3, pp.301-305, September 2004 [1.10] Barbara De Salvo, Cosimo Gerardi, Rob van Schaijk, Savatore A.Lombardo, Domenico Corso, Cristina Plantamura, Stella Serafino, Giuseppe Ammendola, Michiel van Duuren, Pierre Goarin, Wan Yuet Mei, Kees van der Jeugd, Thierry Baron, Marc Gely, Pierre Mur, and Simon Deleonibus, “Performance and Reliability Features of Advanced Nonvolatile Memories Based on Discrete Traps (Silicon Flashs, SONOS),” IEEE Transactions on Device and Materials Reliability, Vol.4, No. 3, pp.377-389, September 2004 [1.11] W. N. Papian, “The MIT magnetic-core memory,” in Proc. Eastern Joint Comp. Conf., Dec. 1953, pp. 37-42 [1.12] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol. 46, no. 4, pp. 1288-1295, 1967 [1.13] T.S. Chen, K.H.Wu, H. Chung, and C.H. Kao, ”Performance Improvement of SONOS Memory by Bandgap Engineering of Charge-Trapping Layer,” IEEE Electron Device Letters, Vol. 25, No. 4, pp.205-207, April 2004 [1.14] Barbara De Salvo, Cosimo Gerardi, Rob van Schaijk, Savatore A.Lombardo, Domenico Corso, Cristina Plantamura, Stella Serafino, Giuseppe Ammendola, Michiel van Duuren, Pierre Goarin, Wan Yuet Mei, Kees van der Jeugd, Thierry Baron, Marc Gely, Pierre Mur, and Simon Deleonibus, “Performance and Reliability Features of Advanced Nonvolatile Memories Based on Discrete Traps (Silicon Flashs, SONOS),” IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 3, pp.377-389, September 2004 [1.15] Stefan Lai, “Flash Memories: Where We Were and Where We are Going,” IEDM Tech. Dig., pp.971-973, 1998 [1.16] Marvin H. White, Dennis A. Adams, and Jiankang Bu, “On the go with SONOS,” IEEE Circuit and Device, pp.22-31, July 2000 [1.17] Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti, “Introduction to Flash Memory,” Proceedings of The IEEE, Vol. 91, No. 4, pp.489-502, April 2003 [1.18] S. Tiwari, F. Rana, K. Chan, H. Hanafi, W. Chan, D. Buchanan,”Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage”, Technical Digest of the IEDM 1995, 521-524 (1995) [1.19] J De Blauwe, “Flash nonvolatile memory devices”, IEEE Trans. Nanotechnol, 2002
[2.1] C.Y. Lu and C.C. Yeh, “Advenced Non-Volatile Memory Devices with Nano-Technology”, Invited Talk for 15th International Conference on Ion Implantation Technology, 2004 [2.2] M. Woods, Nonvolatile Semiconductor Memories: Technologies, Design, and Application, C. Hu, Ed. New York: IEEE Press, (1991) ch. 3, p.59 [2.3] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, 85, 1248 (1997) [2.4] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika and S. Satoh, “Device characteristics of 0.35 m P-channel DINOR flash memory using band-to-band tunneling-induced hot electron (BBHE) programming”, IEEE Trans. Electron Devices, Vol. 46, pp. 1866-1871, (1999) [2.5] J. Bu, and M. H. White, “Design considerations in scaled SONOS nonvolatile memory devices”, Solid-State Electronics., 45, 113 (2001) [2.6] M. L. French, and M. H. White, “Scaling of multidielectric nonvolatile SONOS memory structures”, Solid-State Electron., p.1913 (1994) [2.7] M. L. French, C. Y. Chen, H. Sathianathan, M. H. White., “Design and Scaling of a SONOS Multidielectric Device for Nonvolatile Memory Applications”, IEEE Trans Comp Pack and Manu Tech part A., 17, 390 (1994) [2.8] Y. S. Hisamune, K. Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, A. Ishitani, and T. Okazawa, “A high capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbitand future flash memories”, IEDM Tech. Dig., p.19 (1993) [2.9] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview”, Proceedings of The IEEE, 85, 1248 (1997) [2.10] D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, “Statistical model of reliability and scaling projections for Flash memories,” in IEDM Tech. Dig., 2001, pp.32.2.1–32.2.4. [2.11] D. Ielmini, A. S. Spinelli, A. L. Lacaita, L. Confalonieri, and A. Visconti,“New technique for fast characterization of SILC distribution in Flash arrays,” in Proc. IRPS, 2001, pp. 73–80. [2.12] D. Ielmini, A. S. Spinelli, A. L. Lacaita, R. Leone, and A. Visconti, “Localization of SILC in Flash memories after program/erase cycling,” in Proc. IRPS, 2002, pp. 1–6. [2.13] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, “Failure mechanisms of flash cell in program/erase cycling,” IEDM Tech. Dig., p.291 (1994) [2.14] Y. M. Niquet, G. Allan, C. Delerue and M. Lannoo, “Quantum confinement in Ge nanocrystals,” Appl. Phys. Lett., 77, pp.1182-1184 (2000) [2.15] T. Takagahara and K.Takeda, “Theory of the quantum confinement effect on excitons in quantum dots of indirect- gap materials,” Phys. Rev. B, Vol. 46, p. 15578, 1992 [2.16] J.D.Jackson, “Classcial Electrodynamics”, published by John Wiley & Sons, 1999.
[3.1] Ryuji Ohba, Naoharu Sugiyama,Junji Koga,Shinobu Fujita, “Silicon nitride trap memory with double tunnel junction”,Symposium on VLSI Technology Digest of Technical Papers, p.35-36 (2003) [3.2] C. H. Lai, A. Chin, K. C. Chiang, W. J. Yoo, C. F. Cheng,S. P. McAlister, C. C. Chi and P. Wu, Symp. on VLSI Tech.Dig., 2005, pp. 210-211. [3.3] A. Chin, C. C. Laio, C. Chen, K. C. Chiang, D. S. Yu, W. J.Yoo, G. S. Samudra, T. Wang, I . J . Hsieh, S. P. McAlister,and C. C. Chi, IEDM Tech. Dig., 2005, pp. 165-168 [3.4] C. H. Lai, A. Chin, H. L. Kao, K. M. Chen, M. Hong, J.Kwo and C. C. Chi, Symp. on VLSI Tech. Dig., 2006, pp.54-55 [3.5] S. H. Lin, Albert Chin, F. S. Yeh, and S. P. McAlister,IEDM Tech. Dig., 2008, pp. 843-846 [3.6] H. T. Lue et al, IEDM Tech. Dig., 2005, pp. 547-550 [3.7] K. H. Joo, C. R. Moon, S. N. Lee, X. Wang, J. K. Yang, I.S. Yeo, D. Lee, O. Nam,U. I. Chung, J. T. Moon, and B. I.Ryu, IEDM Tech. Dig., 2006, pp. 979–982 [3.8] Albert Chin, S. H. Lin, K. C. Chiang, and F. S. Yeh, “Improved Device Characteristics in Charge-Trapping-Engineered Flash Memory Using high-κDielectrics,” ECS Trans., vol. 25, no. 6, pp. 447-455, 200
[4.1] M. L. Lee, Z.Y. Cheng, C. W. Leitz, A. J. Pitera, T. A. Langdo, M. T.Currie, G. Taraschi, E. A. Fitzgerald, and D. A. Antoniadis, Appl. Phys.Lett. 79, 3344 ,2001 [4.2] S. Takagi, Tech. Dig. VLSI Symp. 2003, 115 [4.3] Y. C. King, T. J. King, and C. Hu, IEEE Electron Device Lett. 20, 409, 1999. [4.4] L. Dori, A. Acovic, D. J. Dimaria, and C. H. Hsu, IEEE Electron Device Lett. 14, 283, 1993. [4.5] M. Rosmeulen, E. Sleeckx, and K. D. Meyer, Tech. Dig. - Int. Electron Devices Meet. 2002, 189. [4.6] C.H. Tu , T.C. Chang, P.T. Liu, H.C. Liu, W.R. Chen, C.C. Tsai, L.T. Chang, and C.Y. Chang, “Formation of silicon germanium nitride layer with distributed charge storage elements,” Appl. Phys. Lett. 88, 112105,2006
[5.1] C.H. Tu , T.C. Chang, P.T. Liu, H.C. Liu, W.R. Chen, C.C. Tsai, L.T. Chang, and C.Y. Chang, “Formation of silicon germanium nitride layer with distributed charge storage elements,” Appl. Phys. Lett. 88, 112105,2006 [5.2] J. Am. Ceram. Soc., 85, 75, 2002 [5.3] Jianjun Dong, Jack Deslippe, Otto F. Sankey, Emmanuel Soignard, and Paul F. McMillan, “Theoretical study of the ternary spinel nitride system Si3N4-Ge3N4,” Physical review b 67, 094104 ~2003! [5.4] H. Wang, Y. Chen, Yasunori Kaneta, and Shuichi Iwata, “First-principles investigation of structural, electronic and optical properties of IVA group spinel nitrides” Eur. Phys. J. B 59, 155–165, 2007 [5.5] W. Y. Ching, Shang-Di Mo, and Lizhi Ouyang, “Electronic and optical properties of the cubic spinel phase of c-Si3N4, c-Ge3N4, c-SiGe2N4, and c-GeSi2N4” physical review b, volume 63, 245110 [5.6] A. Bouhemadou1,a, Y. Al-Douri2, R. Khenata3, and K. Haddadi1, “Structural, elastic, electronic, optical and thermal properties of c-SiGe2N4” Eur. Phys. J. B 71, 185–194, 2009
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