臺灣博碩士論文加值系統

本文以階層式、模組化方法設計了JPEG2000編解碼器，並且以FPGA實現硬體的驗證。該編解碼器包括了離散小波轉換、量化及EBCOT Tier-1的編碼和解碼模組。在精簡硬體資源的前提下，我們針對每一個模組提出高性能的運算架構，並採用GRAFCET建立演算法的離散事件模型。最後以硬體合成方法論生成硬體功能方塊的整合控制器電路，使得此一編解碼器具有良好的分散式架構和可擴充性，並且易於進行系統整合。實驗顯示，在更少的硬體資源需求下，我們的JPEG2000編解碼器可達到每秒20幅512x512大小的影像的編/解碼效能。

The hierarchical modular design and hardware implementation of JPEG2000 codec are presented in this thesis. The codec includes three major modules: DWT, Quantizer, and EBCOT Tier-1. On the premise of reducing the hardware resources requirement, we elaborate a high-performance architecture and discrete-event model for each functional module. Through the hardware synthesis methodology, the RTL hardware of each functional module is generated rapidly. The synthesized circuit possesses distributed architecture, good extensibility and ease to system integration. The experiment result shows the proposed JPEG2000 codec can achieve a satisfactory performance of 20 frames/sec coding/decoding speed on 512x512 format image with reduced resources requirement.

中文摘要 II
英文摘要 III
目錄 IV
圖目錄 VI
表目錄 XI

第一章 緒論 1
1.1 JPEG2000 簡介 1
1.2複雜系統設計與硬體合成 3
1.3 論文架構 7
第二章 色彩轉換與量化 8
2.1 色彩轉換 8
2.2 量化 9
2.3 色彩轉換與量化器之硬體驗證 11
第三章 離散小波轉換 14
3.1 提升式結構（Lifting Scheme） 14
3.2 二維離散小波轉換 18
3.3 離散小波轉換之硬體架構 19
第四章 位元平面編碼 28
4.1 EBCOT中的區塊編碼 28
4.1.1 位元平面編碼之四種編碼 31
4.1.2 位元平面編碼的三個編碼程序 34
4.1.3 編碼範例 37
4.2 EBCOT中的區塊解碼 43
4.2.1 解碼範例 46
4.3 位元平面編碼之硬體架構 50
4.3.1 記憶體的架構 51
4.3.2 相鄰標記產生器的設計 56
4.4 位元平面解碼之硬體架構 63
第五章 算數編解碼 73
5.1 MQ-coder編碼流程 73
5.1.1 ENCODE模組 75
5.1.2 RENORME正規化模組 78
5.1.3 BYTEOUT壓縮資料輸出模組 79
5.1.4 INITENC編碼初始化模組 80
5.1.5 FLUSH出清編碼模組 81
5.2 MQ-coder解碼流程 83
5.2.1 DECODE 模組 84
5.2.2 RENORMD解碼正規化模組 86
5.2.3 BYTEIN壓縮資料輸入模組 87
5.2.4 INITDEC解碼初始化模組 88
5.3 預測機率之查表方法 89
5.4 MQ-coder 硬體設計 92
5.4.1 編碼模組硬體架構 92
5.4.2 解碼模組硬體架構 98
5.5結果 103
第六章 系統整合 105
第七章 結論 111
參考文獻 112

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