臺灣博碩士論文加值系統

本篇論文係針對一高速無線區域網路系統HIPERLAN(High PERformance Radio LAN)接收端的可適應性決策回授等化器，從事相關的設計及製作。
一方面從系統的觀點出發，利用電腦模擬的方式完成等化器的架構設計、效能分析、和信號有限位元長度的決定，一方面從硬體製作的角度開始，利用SPW(Signal Processing WorkSystem)、VA(Visual Architect)等軟體，先後完成等化器硬體的預先模擬和RTL硬體語言的轉換，以進一步的從事gate level電路的合成設計。

The design and implementation of an Adaptive Decision Feedback Equalizer(ADFE) applicable to the receiver of the HIPERLAN(High Performance Radio LAN) system is investigated. computer simulations are used to design the parameters of the proposed equalizer architecture, including number of taps, step size, and the word length of input signal and coefficients of equalizer, from the standpoint of HIPERLAN physical layer performance. In addition, SPW(Signal Processing WorkSystem) is employed to verify the equalizer algorithm and architecture, and then the RTL codes are optimized and transferred by VA(Visual Architect) for the gate level circuit implementation of equalizer from a hardware standpoint.

內容
第一章 緒論 1
第二章 系統簡介與等化器選擇考量 3
2.1 傳送器架構 3
2.1.1 GMSK調變及線性近似理論分析 3
2.1.2 HIPERLAN資料封包架構 7
2.2 模擬時所使用的通道架構 8
2.3 接收器架構 9
2.3.1 載波頻率偏移估計與符元時脈回復 9
2.3.2 可適應性決策回授等化器 10
第三章 等化器設計流程與模擬分析 18
3.1 設計流程18
3.2 模擬分析19
第四章 功能設計與模擬 28
4.1 Floating point 模擬 29
4.1.1 HBR 系統部分 29
4.1.2 LBR 系統部分 31
4.2 Fixed point 模擬 32
第五章 硬體語言合成與最佳化 46
5.1 Visual Architect之設計考量 46
5.1.1 格式要求46
5.1.2 設計及最佳化流程 47
5.1.3 電路特性分析與比較 50
第六章結論58
附錄 59
參考文獻 61

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