臺灣博碩士論文加值系統

三維堆疊近來已成為一個積體電路相當流行的技術，而其中基於矽中介層的三維堆疊電路是在業界的主要趨勢，尤其是應用在處理器與記憶體的堆疊。去評估且找出基於矽中介層的三維堆疊最具經濟效益的測試流程是很重要的。我們提出了一個基於矽中介層的三維堆疊電路的成本模型，並且包括了晶片到晶圓 (D2W) 和晶片到晶片 (D2D) 兩種堆疊方式，成本裡也包含了製造成本和測試成本。我們將成本模型實作成成本分析工具，且使用此工具尋找最具經濟效益的測試流程。從結果我們可以發現，在某些應用中，測試流程若有包含反覆的堆疊測試 (iterative KGS test) 和矽中介層堆疊前測試 (pre-bond interposer test)，當堆疊良率低於99.2%和矽中介層良率低於99%時可以顯著地減少成本。另外也描繪了一個Shmoo圖表示在不同產品良率以及堆疊晶片顆數下所需封裝測試良率的底限。而三種不同的三維記憶體修復方案的成本也做了比較，結果表示當備用晶片數目大於二十顆時，使用區塊層級備分記憶體 (macro level redundancy) 可以得到最低的成本。對於不同的應用，該模型可找出測試動作執行的標準以及計算出成本值，這也可以幫助工程師去找出最具經濟效益的測試流程與系統架構。

Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for interposer-based 3D IC with 3D memory repair schemes, including the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking. The cost model contains the manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 99.2% and the pre-bond interposer test yield is lower than 99%. The Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. The total costs of three types of 3D memory repair schemes are compared. The result shows that, among three different 3D memory repair schemes, the macro level redundancy with over 20 redundancy dies has the lowest cost. For different applications, the proposed model evaluates the execution criterion or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.

Abstract i
1 Introduction 1
1.1 Three-Dimensional (3D) IC Integration………………………………… 1
1.2 Interposer-Based 3D IC………………………………………………… 1
1.3 Previous Works of 3D IC Testing Flow and Cost Model………………... 2
1.4 Motivations and Contributions…………………………………………… 3
1.5 Organization of the Thesis………………………………………………4
2 Interposer-Based Three Dimensional (3-D) Integration Technology 5
2.1 Wire Bonded Technology……………………………………………… 5
2.2 Interposer Technology…………………………………………………… 6
2.2.1 Micro-Bump Technology…………………………………………… 6
2.2.2 Through-Silicon Via (TSV) Technology…………………………… 7
2.2.3 Controlled Collapse Chip Connection (C4) Bump Technology…… 7
2.3 Stacking Styles…………………………………………………………… 8
2.4 Related Works of Cost Models for 2D/3D ICs………………………… 9
2.4.1 Cost Models for 2D ICs…………………………………………… 9
2.4.2 Cost Models for 3D ICs…………………………………………… 10
3 Memory Repair Architecture 12
3.1 Memory Built-In-Self-Repair (MBISR) Designs……………………… 12
3.2 Review of Memory Repair Analysis Algorithms……………………… 14
3.2.1 Row/Column-First Repair Algorithm…………………………… 14
3.2.2 Essential Spare Pivoting (ESP) Repair Algorithm……………… 15
3.3 Memory Repair Architecture for 3D Memory Cube…………………… 15
3.3.1 Global Redundancy……………………………………………… 15
3.3.2 Die-Level Redundancy…………………………………………… 16
3.3.3 Macro-Level Redundancy………………………………………… 18
iii
4 Production Flow for Interposer-Based 3D IC 20
4.1 Manufacturing Flow…………………………………………………… 20
4.2 Test Flow……………………………………………………………… 22
4.3 Previous Works in 3D IC Testing……………………………………… 26
4.4 The Frameworks of Test Flows………………………………………… 27
5 Cost Model for Interposer-Based 3D ICs 29
5.1 Manufacturing Cost Model……………………………………………30
5.2 Test Cost Model………………………………………………………… 32
5.3 Repair-Based Memory Cube Cost Model……………………………… 39
6 Cost Evaluation 42
6.1 Evaluation Flow………………………………………………………… 42
6.2 Bitmap Generator………………………………………………………43
6.3 3D Redundancy Analysis (3D-RA) Simulator…………………………44
6.4 Cost Evaluator……………………………………………………………44
7 Experimental Results 47
7.1 Background and Model Parameters……………………………………47
7.2 Cost Comparison of Different Test Flows……………………………… 49
7.3 The Shmoo Plot of Needed Final Test Yield ……………………………53
7.4 Cost Comparison of Different Memory Redundancy Architectures ……54
8 Conclusions and Future Work 59
8.1 Conclusions ……………………………………………………………59
8.2 Future Work ……………………………………………………………60

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