臺灣博碩士論文加值系統

本篇論文主要是對低雜訊放大器與混頻器理論架構進行探討，並就其設計模擬。最後並對近年來操作在5 GHz左右的混頻器特性參數列表整理，以比較各個混頻器效能的好壞。
所設計的第一個低雜訊放大器以global feedback pairs為基礎架構，以電晶體取代串連回授的電阻，在第一級與第二級電路間串接一電感，來達到增益平坦的效果，輸出端除了做為RF choke的電感外，以一電晶體來達到寬頻的阻抗匹配。此LNA可以操作在2.4 GHz~6 GHz之間，頻寬涵蓋了IEEE 802.11a與IEEE 802.11b的頻率範圍。第二個低雜訊放大器是以低雜訊、高增益為目標，對第一級的電晶體做S參數模擬，找出其寬度與偏壓對電流、雜訊、增益的關係，選擇出一合適的偏壓與電晶體寬度，第二級為cascade架構，以內部串聯諧振的方式來提升其增益，此LNA可操作在3~6GHz，增益為24~25.5dB，雜訊則是在0.8~1.1dB之間。
在混頻器方面，第一個單端輸入單端輸出混頻器架構裡，在輸入端採用微混頻器的技術，輸出端採用current combiner的方法，此混頻器可以操作在2.3 GHz~6 GHz，擁有2.7 GHz的頻寬，涵蓋了IEEE 802.11a與IEEE 802.11b的頻率範圍，在此頻寬內，增益均大於0 dB，IIP3介在9.5~12 dBm之間，雜訊指數則是介於16~18 dB，消耗功率為8.55 mW。第二個電路架構，是由降低輸入的本地振盪訊號頻率的想法所設計的，將LO的頻率減半，以連續降頻的方式將RF的訊號降至基頻，其增益為2 dB，IIP3為4.89 dBm，雜訊指數為12.6 dB，消耗功率為15.5 mW。
上述電路是利用tsmc 0.18um CMOS 製程所設計，模擬軟體為Agilent ADS 2005A。

誌謝 .................................................... i
中文摘要 ............................................... ii
英文摘要 ............................................... iv
目錄 .................................................... v
圖目錄 ............................................... viii
表目錄 ..................................................... xi
第一章 序論
1.1 研究背景 ............................................ 1
1.2 接收機積體電路架構介紹 .............................. 3
1.3 論文架構 ............................................ 4
第二章 混頻器分析
2.1 超外差式混頻器 ...................................... 5
2.2 雙降頻式超外差混頻器 ................................ 6
2.3 直接降頻式混頻器 .................................... 7
2.4 討論 ............................................... 10
第三章 接收機重要規格參數
3.1 轉換增益/損耗(Conversion Gain/Loss) ................ 12
3.2 1dB壓縮點(P1dB) .................................... 12
3.3 輸入三階截斷點(IIP3) ............................... 14
3.4 雜訊指數(Noise Figure) ............................. 16
3.5 輸入返回損耗(return loss) .......................... 18
3.6 隔離度(Isolation) .................................. 18
3.7 功率消耗(power consumption) ........................ 19
第四章 兩級寬頻低雜訊放大器電路設計
4.1 低雜訊放大器基本架構 ............................... 20
4.2 回授型低雜訊放大器(LNA)架構 ........................ 21
4.3 寬頻回授LNA電路設計 ................................ 22
4.3.1電路架構 .......................................... 22
4.3.2 模擬結果 ......................................... 24
4.4 寬頻高增益LNA電路設計 .............................. 30
4.4.1電路架構 .......................................... 30
4.4.2 模擬結果 ......................................... 31
第五章 混頻器架構說明
5.1 混頻器簡介 ......................................... 38
5.2 混頻器種類 ......................................... 38
5.2.1 被動式混頻器 ..................................... 38
5.2.2 主動式混頻器 ..................................... 39
5.3 單平衡式混頻器架構 ................................. 39
5.4 雙平衡式Gibert Cell混頻器架構 ...................... 41
5.5 常見的設計技巧 ..................................... 44
5.5.1 Current bleeding ................................. 44
5.5.2 差動訊號轉換成單端訊號 ........................... 44
5.5.3 提高線性度 ....................................... 46
5.5.4 微混頻器(Micro-mixer) ............................ 49
第六章 混頻器電路設計
6.1 Mixer 1 : 單端輸入單端輸出外差式混頻器 ............. 51
6.2 模擬結果 ........................................... 53
6.3 Mixer 2 : 兩次降頻混頻器電路設計 ................... 61
6.4 模擬結果 ........................................... 62
第七章 結論與未來研究方向 .............................. 66
參考文獻 ............................................... 68

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