臺灣博碩士論文加值系統

半導體製造技術的進步使得 feature size 不斷的縮小，帶來了晶片系統高度整合與效能的提升。採用 flip-chip 的晶片封裝技術減輕了傳統 wire-bonding 晶片封裝技術對整體晶片效能所帶來的衝擊。然而，在IO 數量持續攀升的情況下，晶片封裝必須考量信號品質、電壓降、靜電防護等重要議題，使得 IO 的 design rule 越來越複雜。傳統針對 package routability 優化的 bump 擺放方式已無法有效克服先進製程的挑戰。在本論文裡，我們分別提出了 heuristics for IO/Bump placement 及 dynamic programming based IO/Bump placement。藉由滿足 design rule 的 IO sequence來完成初版的 IO/Bump placement，並且加入 bump pitch 來保留足夠的 package routing 空間，保證了 IO/Bump placement 結果的package routability。由於 IO 總寬度有效地被減少，不僅能增進晶片的 RDL routability，在後期也有機會利用省下的空間提供 decoupling capacitor 對於晶片內部的電源補強，以改進晶片的 voltage drop。
在實驗結果中，我們使用 centered-style dynamic programming based IO/Bump placement，平均比 heuristics for IO/Bump placement 減少 65.51% IO 被撐開的寬度，並比使用 right-edge-style dynamic programming based IO/Bump placement 平均減少 59.84% 的 X 方向 routing 距離。最後，我們更提出 non-aligned-style (left-edge) IO/Bump placement，平均使得 dynamic programming based IO/Bump placement 被撐開的寬度比原本 right-edge-style 的結果再縮小 57.53%，甚至 X 方向 routing 距離在 heuristics for IO/Bump placement 中可以減少 51.14%。

The advancement of technology scaling enables high-level system integration and performance enhancement. With the flip-chip technology, we are able to alleviate the wire-bonding R/L/C impact to an integrated circuit. However, as the increasing of total number of chip IOs, IC packaging is required to simultaneously take signal integrity, voltage drop, and electrostatic protection into account. Consequently, the design rules for flip-chip IO become more complex. Traditional routability-driven bump placement may not be effective to overcome the aforementioned challenges nowadays. In this thesis, we propose heuristic algorithms for IO/Bump placement, and dynamic programming based IO/Bump placement algorithms for IO pads and bumps co-design problem. With our proposed technique, the total IO width is reduced for RDL routability enhancement and decoupling capacitor insertion to reduce voltage drop.
According to the experimental results, our centered-style dynamic programming based IO/Bump placement reduces the extended IO width by 65.51% and the x-direction routing distance is reduced by 59.84%. Finally, if the non-aligned-style (left-edge) IO/bump alignment is allowed, the extended IO width could be further reduced by 57.53%. With the heuristics for IO/Bump placement, the x-direction routing distance is reduced by 51.14%.

中文摘要 III
ABSTRACT IV
誌 謝 V
圖目錄 VIII
表目錄 X
第一章、 研究簡介 1
1.1 晶片製造 1
1.2 晶片封裝 3
第二章、 研究背景與動機 5
2.1 研究背景 5
2.2 研究動機 9
2.3 NAÏVE IO/BUMP PLACEMENT 12
2.3.1 Right-edge-style Design 13
2.3.2 Centered-style Design 18
第三章、 文獻探討 22
3.1 RDL DESIGN 22
3.2 PACKAGE DESIGN 24
3.3 RDL AND PACKAGE CO-DESIGN 25
第四章、 研究問題 26
第五章、 研究方法 29
5.1 HEURISTICS FOR IO/BUMP PLACEMENT 29
5.1.1 Right-edge-style Design 31
5.1.2 Centered-style Design 34
5.2 DYNAMIC PROGRAMMING BASED IO/BUMP PLACEMENT 39
5.2.1 Right-edge-style Design 40
5.2.2 Centered-style Design 45
5.3 NON-ALIGNED-STYLE IO/BUMP PLACEMENT 49
5.3.1 Heuristics for IO/Bump Placement 50
5.3.2 Dynamic Programming Based IO/Bump Placement 57
5.4 研究方法範例分析 64
5.5 IO/BUMP PLACEMENT 研究限制 67
第六章、 實驗結果 68
6.1 實驗環境 68
6.2 IO 總寬度的比較與分析 70
6.3 RDL ROUTING 距離的比較與分析 73
6.4 NON-ALIGNED-STYLE IO/BUMP PLACEMENT 的比較與分析 77
6.5 VOLTAGE DROP 的比較與分析 83
第七章、 結論和 FUTURE WORK 87
參考文獻 89

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